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11.发明授权Semiconductor device testing apparatus, system, and method for testing the contacting with semiconductor devices positioned one upon the other 有权用于测试与另一个定位的半导体器件的接触的半导体器件测试装置，系统和方法公开(公告)号：US07251758B2
公开(公告)日：2007-07-31
申请号：US10738118
申请日：2003-12-18
申请人： Christian Stocken , Manfred Dobler
发明人： Christian Stocken , Manfred Dobler
IPC分类号： G11C29/00
CPC分类号： G11C29/022 , G11C29/02
摘要： A semiconductor device testing apparatus, system, and method, in particular for testing the contacting with semiconductor devices positioned one upon the other, wherein at least two semiconductor devices are provided that are connected to a device module, at least one pin of a first semiconductor device is conductively connected with a pad, and at least one pin of a second semiconductor device also is to conductively connected with the pad. A first value is written into a memory cell of the first semiconductor device, a second value differing from the first value is written into a memory cell of the second semiconductor device, and a signal corresponding to the first value at the pin of the first semiconductor device and of a signal corresponding to the second value at the pin of the second semiconductor device is simultaneously output.
摘要翻译： 一种半导体器件测试装置，系统和方法，特别是用于测试与彼此定位的半导体器件的接触，其中提供至少两个半导体器件，其连接到器件模块，第一半导体的至少一个引脚 器件与衬垫导电连接，并且第二半导体器件的至少一个引脚也与衬垫导电连接。 将第一值写入第一半导体器件的存储单元中，将与第一值不同的第二值写入第二半导体器件的存储单元中，并且将与第一半导体器件的引脚处的第一值相对应的信号 并且同时输出与第二半导体器件的引脚处的第二值对应的信号。
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公开(公告)号：US20060277379A1
公开(公告)日：2006-12-07
申请号：US11414554
申请日：2006-05-01
CPC分类号： G11C7/1045 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/408
摘要： An integrated semiconductor memory device includes a first memory zone, a second memory zone, first address connections and a second address connection. A second address signal present at the second address connection specifies the access to the first or second memory zone, whereas it is specified via first address signals at the first address connections which memory cell is accessed within the first or second memory zone. In a first memory configuration, all address connections are driven externally with address signals and the access to a memory cell in the first or second memory zone is controlled. In a second memory configuration, only the first address connections are driven externally whereas a signaling bit in a mode register regulates the access to the first or second memory zone. This provides for access to the second memory zone even if there is no possibility of externally driving the second address connection.
摘要翻译： 集成半导体存储器件包括第一存储区，第二存储区，第一地址连接和第二地址连接。 存在于第二地址连接处的第二地址信号指定对第一或第二存储器区域的访问，而通过第一地址连接处的第一地址信号指定在第一或第二存储器区域内访问哪个存储器单元。 在第一存储器配置中，所有地址连接由地址信号从外部驱动，并且控制对第一或第二存储器区域中的存储器单元的访问。 在第二存储器配置中，仅第一地址连接从外部驱动，而模式寄存器中的信令位调节对第一或第二存储器区的访问。 即使不存在外部驱动第二地址连接的可能性，也可以访问第二存储区域。
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公开(公告)号：US07246278B2
公开(公告)日：2007-07-17
申请号：US10949935
申请日：2004-09-24
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C2029/0407 , G11C2029/5602
摘要： An apparatus (1) for testing a memory module (2) suitable for exchanging electrical signals with a motherboard (10) contains a device (8a–8k) suitable for detecting the operating state of at least one semiconductor chip (26a–26m) of the module, which device comprises a first set of signal lines (8a–8k), a microcontroller (3) with a memory device (32) for storing the operating state, said microcontroller being electrically connected to the signal lines (8a–8k), a clock generator (5) suitable for generating an operating clock, said clock generator being electrically connected to the microcontroller (3), and a signal connection (13) suitable for communicating a signal for controlling access to the memory module (2) between the circuit board arrangement (10) and the microcontroller (3) and for communicating to the microcontroller (3) a signal for initiating a process of detecting the operating state.
摘要翻译： 一种用于测试适合于与主板（10）交换电信号的存储器模块（2）的装置（1），其包含适合于检测至少一个半导体芯片（26a- 26m），该装置包括第一组信号线（8a-8k），具有用于存储操作状态的存储器件（32）的微控制器（3），所述微控制器电连接到信号 线路（8a-8k），适于产生工作时钟的时钟发生器（5），所述时钟发生器电连接到微控制器（3），以及信号连接（13），适于传送用于控制访问的信号 到电路板装置（10）和微控制器（3）之间的存储器模块（2）并且用于与微控制器（3）通信用于启动检测操作状态的过程的信号。
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公开(公告)号：US20060179397A1
公开(公告)日：2006-08-10
申请号：US11300596
申请日：2005-12-15
IPC分类号： G11C29/00
CPC分类号： G06F11/1008
摘要： An error code is generated by generating error correction data from a data sequence. These error correction data together with the data sequence are then written to a memory unit so as to be read from the memory unit. During the reading or during the writing, one bit in the data sequence has its content changed. This induces a bit error from which an error code is generated which can be clearly associated with the bit error. An interface arrangement can be inserted between a computer and a memory module. The interface arrangement contains data lines that are coupled to an apparatus which is designed to generate bit errors during a write or read operation.
摘要翻译： 通过从数据序列生成纠错数据来产生错误代码。 然后将这些纠错数据与数据序列一起写入存储器单元，以便从存储器单元读取。 在读取或写入期间，数据序列中的一位内容发生变化。 这引起了一个错误代码，可以从中产生一个可以与位错误清楚相关的错误代码。 可以在计算机和存储器模块之间插入接口装置。 该接口装置包含耦合到设计用于在写入或读取操作期间产生位错误的装置的数据线。
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公开(公告)号：US20060163600A1
公开(公告)日：2006-07-27
申请号：US11304491
申请日：2005-12-15
CPC分类号： H01L23/5258 , H01L22/22 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014
摘要： A chip component (1) includes a semiconductor body (2), in which at least one switchable element (6, 62) is arranged in a partial region (24) of the semiconductor body (2). The partial region (24) can be reached by light of at least one wavelength. Furthermore, a circuit (9) integrated into the semiconductor body (2) is provided, which integrated circuit can assume one configuration from at least two possible configurations, one of these configurations being prescribed by a state of the at least one switchable element (6, 62). Furthermore, a housing (3) is provided, which encloses the semiconductor body (2) and is arranged with a partial region (35, 32) at least partly above the partial region (24) of the semiconductor body (2). The partial region (35, 32) of the housing (3) is formed in such a way that light can be fed to the partial region (24) of the semiconductor body (2). It is thus possible even after a fabrication process to carry out a test and, if appropriate, to define a different configuration through switching of the element (6, 62).
摘要翻译： 芯片部件（1）包括半导体本体（2），其中至少一个可切换元件（6,62）布置在半导体主体（2）的部分区域（24）中。 部分区域（24）可以通过至少一个波长的光达到。 此外，集成在半导体本体（2）中的电路（9）被设置，该集成电路可以从至少两个可能的配置呈现一个配置，这些配置中的一个由至少一个可切换元件（6）的状态 ，62）。 此外，设置有壳体（3），其包围半导体本体（2）并且布置有至少部分地在半导体主体（2）的部分区域（24）之上的部分区域（35,32）。 壳体（3）的部分区域（35,32）形成为能够将光馈送到半导体本体（2）的部分区域（24）的方式。 因此，即使在制造过程之后进行测试也是可能的，并且如果适当的话通过切换元件（6,62）来定义不同的配置。
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公开(公告)号：US07023701B2
公开(公告)日：2006-04-04
申请号：US10829362
申请日：2004-04-22
IPC分类号： H05K7/20
CPC分类号： H01L23/367 , G06F1/20 , H01L23/4338 , H01L2924/0002 , H01L2924/00
摘要： A device for cooling memory modules can include a plurality of elements. The elements can thermal couple at least two memory modules. The device can further include a body or a plurality of contact areas bearing in a planar manner.
摘要翻译： 用于冷却存储器模块的装置可以包括多个元件。 元件可以热耦合至少两个存储器模块。 该装置还可包括以平面方式支承的主体或多个接触区域。
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公开(公告)号：US20050251728A1
公开(公告)日：2005-11-10
申请号：US11116197
申请日：2005-04-28
申请人： Christian Stocken
发明人： Christian Stocken
CPC分类号： G11C29/42
摘要： A test arrangement with a test memory chip and a control device is provided, which has a first and a second interface. The test arrangement is connected to a memory slot of a computer system and is connected by its second interface to a memory module. Error correction data that are written to the error correction chip of the memory module by a memory controller of the computer system are stored in the test memory chip with the aid of the control device. In the case of an error event, it is ascertained whether the error occurred on the error correction chip. If this is the case, the memory controller compares the data stored in the error correction chip with the data of the auxiliary memory. The address of the error correction chip can be deduced from the address of the auxiliary memory, thereby enabling unambiguous addressing of a defective memory cell of the error correction chip.
摘要翻译： 提供了具有测试存储器芯片和控制装置的测试装置，其具有第一和第二接口。 测试装置连接到计算机系统的存储器插槽，并通过其第二接口连接到存储器模块。 由计算机系统的存储器控制器写入存储器模块的纠错芯片的纠错数据通过控制装置存储在测试存储器芯片中。 在错误事件的情况下，确定错误是否发生在纠错芯片上。 如果是这种情况，则存储器控制器将存储在纠错芯片中的数据与辅助存储器的数据进行比较。 可以从辅助存储器的地址推断出纠错芯片的地址，从而能够对错误校正芯片的缺陷存储单元进行明确的寻址。
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公开(公告)号：US20050018401A1
公开(公告)日：2005-01-27
申请号：US10829362
申请日：2004-04-22
IPC分类号： G06F1/20 , H01L23/367 , H01L23/433 , H05K7/20
CPC分类号： H01L23/367 , G06F1/20 , H01L23/4338 , H01L2924/0002 , H01L2924/00
摘要： A device for cooling memory modules can include a plurality of elements. The elements can thermal couple at least two memory modules. The device can further include a body or a plurality of contact areas bearing in a planar manner.
摘要翻译： 用于冷却存储器模块的装置可以包括多个元件。 元件可以热耦合至少两个存储器模块。 该装置还可包括以平面方式支承的主体或多个接触区域。
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