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公开(公告)号：US07291902B2
公开(公告)日：2007-11-06
申请号：US11304491
申请日：2005-12-15
IPC分类号： H01L23/02
CPC分类号： H01L23/5258 , H01L22/22 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014
摘要： A chip component (1) includes a semiconductor body (2), in which at least one switchable element (6, 62) is arranged in a partial region (24) of the semiconductor body (2). The partial region (24) can be reached by light of at least one wavelength. Furthermore, a circuit (9) integrated into the semiconductor body (2) is provided, which integrated circuit can assume one configuration from at least two possible configurations, one of these configurations being prescribed by a state of the at least one switchable element (6, 62). Furthermore, a housing (3) is provided, which encloses the semiconductor body (2) and is arranged with a partial region (35, 32) at least partly above the partial region (24) of the semiconductor body (2). The partial region (35, 32) of the housing (3) is formed in such a way that light can be fed to the partial region (24) of the semiconductor body (2). It is thus possible even after a fabrication process to carry out a test and, if appropriate, to define a different configuration through switching of the element (6, 62).
摘要翻译： 芯片部件（1）包括半导体本体（2），其中至少一个可切换元件（6,62）布置在半导体主体（2）的部分区域（24）中。 部分区域（24）可以通过至少一个波长的光达到。 此外，集成在半导体本体（2）中的电路（9）被设置，该集成电路可以从至少两个可能的配置呈现一个配置，这些配置中的一个由至少一个可切换元件（6）的状态 ，62）。 此外，设置有壳体（3），其包围半导体本体（2）并且布置有至少部分地在半导体主体（2）的部分区域（24）之上的部分区域（35,32）。 壳体（3）的部分区域（35,32）形成为能够将光馈送到半导体本体（2）的部分区域（24）的方式。 因此，即使在制造过程之后进行测试也是可能的，并且如果适当的话通过切换元件（6,62）来定义不同的配置。
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公开(公告)号：US20060179397A1
公开(公告)日：2006-08-10
申请号：US11300596
申请日：2005-12-15
IPC分类号： G11C29/00
CPC分类号： G06F11/1008
摘要： An error code is generated by generating error correction data from a data sequence. These error correction data together with the data sequence are then written to a memory unit so as to be read from the memory unit. During the reading or during the writing, one bit in the data sequence has its content changed. This induces a bit error from which an error code is generated which can be clearly associated with the bit error. An interface arrangement can be inserted between a computer and a memory module. The interface arrangement contains data lines that are coupled to an apparatus which is designed to generate bit errors during a write or read operation.
摘要翻译： 通过从数据序列生成纠错数据来产生错误代码。 然后将这些纠错数据与数据序列一起写入存储器单元，以便从存储器单元读取。 在读取或写入期间，数据序列中的一位内容发生变化。 这引起了一个错误代码，可以从中产生一个可以与位错误清楚相关的错误代码。 可以在计算机和存储器模块之间插入接口装置。 该接口装置包含耦合到设计用于在写入或读取操作期间产生位错误的装置的数据线。
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公开(公告)号：US20060163600A1
公开(公告)日：2006-07-27
申请号：US11304491
申请日：2005-12-15
CPC分类号： H01L23/5258 , H01L22/22 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014
摘要： A chip component (1) includes a semiconductor body (2), in which at least one switchable element (6, 62) is arranged in a partial region (24) of the semiconductor body (2). The partial region (24) can be reached by light of at least one wavelength. Furthermore, a circuit (9) integrated into the semiconductor body (2) is provided, which integrated circuit can assume one configuration from at least two possible configurations, one of these configurations being prescribed by a state of the at least one switchable element (6, 62). Furthermore, a housing (3) is provided, which encloses the semiconductor body (2) and is arranged with a partial region (35, 32) at least partly above the partial region (24) of the semiconductor body (2). The partial region (35, 32) of the housing (3) is formed in such a way that light can be fed to the partial region (24) of the semiconductor body (2). It is thus possible even after a fabrication process to carry out a test and, if appropriate, to define a different configuration through switching of the element (6, 62).
摘要翻译： 芯片部件（1）包括半导体本体（2），其中至少一个可切换元件（6,62）布置在半导体主体（2）的部分区域（24）中。 部分区域（24）可以通过至少一个波长的光达到。 此外，集成在半导体本体（2）中的电路（9）被设置，该集成电路可以从至少两个可能的配置呈现一个配置，这些配置中的一个由至少一个可切换元件（6）的状态 ，62）。 此外，设置有壳体（3），其包围半导体本体（2）并且布置有至少部分地在半导体主体（2）的部分区域（24）之上的部分区域（35,32）。 壳体（3）的部分区域（35,32）形成为能够将光馈送到半导体本体（2）的部分区域（24）的方式。 因此，即使在制造过程之后进行测试也是可能的，并且如果适当的话通过切换元件（6,62）来定义不同的配置。
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公开(公告)号：US07272757B2
公开(公告)日：2007-09-18
申请号：US11116197
申请日：2005-04-28
申请人： Christian Stocken
发明人： Christian Stocken
IPC分类号： G11C21/00
CPC分类号： G11C29/42
摘要： A test arrangement with a test memory chip and a control device is provided. Error correction data are stored in the test memory chip with the aid of the control device. In the case of an error event, it is ascertained whether the error occurred on the error correction chip. If so, the memory controller compares the data stored in the error correction chip with the data of the auxiliary memory. The address of the error correction chip can be deduced from the address of the auxiliary memory, thereby enabling unambiguous addressing of a defective memory cell of the error correction chip.
摘要翻译： 提供了具有测试存储器芯片和控制装置的测试装置。 借助控制装置将误差校正数据存储在测试存储器芯片中。 在错误事件的情况下，确定错误是否发生在纠错芯片上。 如果是这样，则存储器控制器将存储在纠错芯片中的数据与辅助存储器的数据进行比较。 可以从辅助存储器的地址推断出纠错芯片的地址，从而能够对错误校正芯片的缺陷存储单元进行明确的寻址。
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公开(公告)号：US07283419B2
公开(公告)日：2007-10-16
申请号：US11414554
申请日：2006-05-01
IPC分类号： G11C8/00
CPC分类号： G11C7/1045 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/408
摘要： An integrated semiconductor memory device includes a first memory zone, a second memory zone, first address connections and a second address connection. A second address signal present at the second address connection specifies the access to the first or second memory zone, whereas it is specified via first address signals at the first address connections which memory cell is accessed within the first or second memory zone. In a first memory configuration, all address connections are driven externally with address signals and the access to a memory cell in the first or second memory zone is controlled. In a second memory configuration, only the first address connections are driven externally whereas a signaling bit in a mode register regulates the access to the first or second memory zone. This provides for access to the second memory zone even if there is no possibility of externally driving the second address connection.
摘要翻译： 集成半导体存储器件包括第一存储区，第二存储区，第一地址连接和第二地址连接。 存在于第二地址连接处的第二地址信号指定对第一或第二存储器区域的访问，而通过第一地址连接处的第一地址信号指定在第一或第二存储器区域内访问哪个存储器单元。 在第一存储器配置中，所有地址连接由地址信号从外部驱动，并且控制对第一或第二存储器区域中的存储器单元的访问。 在第二存储器配置中，仅第一地址连接从外部驱动，而模式寄存器中的信令位调节对第一或第二存储器区的访问。 即使不存在外部驱动第二地址连接的可能性，也可以访问第二存储区域。
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6.发明授权Circuit arrangement having a number of integrated circuit components on a carrier substrate and method for testing a circuit arrangement of this type 有权在载体基板上具有多个集成电路部件的电路装置以及用于测试这种电路装置的方法公开(公告)号：US07251772B2
公开(公告)日：2007-07-31
申请号：US10732402
申请日：2003-12-11
申请人： Christian Stocken , Gerald Resch , Manfred Pröll , Manfred Dobler
发明人： Christian Stocken , Gerald Resch , Manfred Pröll , Manfred Dobler
CPC分类号： G11C29/025 , G11C11/401 , G11C29/02 , G11C29/1201 , G11C2029/5006
摘要： A circuit arrangement can have a number of integrated circuit components, which are arranged on a carrier substrate. A reception circuit for receiving a control signal can be coupled to one of the connection pads on the input side and can be connected to each of the circuit components on the output side. A bridging circuit controlled by a test mode signal can electrically bridge the reception circuit. In a testing method, a plurality of connection pads can be connected to a first potential and at least one of the connection pads can be connected to a second potential. The bridging circuit can be activated and the current measured, by a test arrangement, at the at least one of the connection pads. Inspection for leakage currents in connections between input-side reception circuits and the circuit components can be measured.
摘要翻译： 电路装置可以具有多个集成电路部件，其被布置在载体基板上。 用于接收控制信号的接收电路可以耦合到输入侧的一个连接焊盘，并且可以连接到输出侧的每个电路部件。 由测试模式信号控制的桥接电路可以使接收电路电桥。 在测试方法中，多个连接焊盘可以连接到第一电位，并且至少一个连接焊盘可以连接到第二电位。 可以激活桥接电路，并且通过测试装置在至少一个连接焊盘处测量电流。 可以测量输入侧接收电路和电路部件之间的连接中的漏电流的检查。
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公开(公告)号：US20050138506A1
公开(公告)日：2005-06-23
申请号：US10949935
申请日：2004-09-24
申请人： Christian Stocken , Michael Sommer
发明人： Christian Stocken , Michael Sommer
CPC分类号： G11C29/56 , G11C2029/0407 , G11C2029/5602
摘要： An apparatus (1) for testing a memory module (2) suitable for exchanging electrical signals with a motherboard (10) contains a device (8a-8k) suitable for detecting the operating state of at least one semiconductor chip (26a-26m) of the module, which device comprises a first set of signal lines (8a-8k), a microcontroller (3) with a memory device (32) for storing the operating state, said microcontroller being electrically connected to the signal lines (8a-8k), a clock generator (5) suitable for generating an operating clock, said clock generator being electrically connected to the microcontroller (3), and a signal connection (13) suitable for communicating a signal for controlling access to the memory module (2) between the circuit board arrangement (10) and the microcontroller (3) and for communicating to the microcontroller (3) a signal for initiating a process of detecting the operating state.
摘要翻译： 一种用于测试适合于与主板（10）交换电信号的存储模块（2）的装置（1），其包含适于检测至少一个半导体芯片（26a- 26m），该装置包括第一组信号线（8a-8k），具有用于存储操作状态的存储器件（32）的微控制器（3），所述微控制器电连接到信号 线路（8a-8k），适于产生工作时钟的时钟发生器（5），所述时钟发生器电连接到微控制器（3），以及信号连接（13），适于传送用于控制访问的信号 到电路板装置（10）和微控制器（3）之间的存储器模块（2）并且用于与微控制器（3）通信用于启动检测操作状态的过程的信号。
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公开(公告)号：US07260671B2
公开(公告)日：2007-08-21
申请号：US10278232
申请日：2002-10-23
申请人： Eric Cordes , Christian Stocken , Nazif Taskin , Norbert Wirth
发明人： Eric Cordes , Christian Stocken , Nazif Taskin , Norbert Wirth
IPC分类号： G06K19/10
CPC分类号： G11C7/1045 , G11C5/04 , G11C7/20 , G11C16/20
摘要： A memory module includes at least one memory chip arranged on the memory module. Information about the memory module and/or the at least one memory chip arranged on the memory module can be stored directly on the memory chip, making use of a suited element, fuses or flip-flops, for example. A memory chip contains such an element for containing information relating to the memory chip and/or a memory module with which the memory chip is compatible, wherein the information containing element can be read out by means of an external processor.
摘要翻译： 存储器模块包括布置在存储器模块上的至少一个存储器芯片。 关于存储器模块和/或布置在存储器模块上的至少一个存储器芯片的信息可以直接存储在存储器芯片上，例如使用适合的元件，保险丝或触发器。 存储器芯片包含用于存储与存储器芯片相关的信息的存储器芯片和/或与存储器芯片兼容的存储器模块的元件，其中信息包含元件可以通过外部处理器读出。
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9.发明授权Housing for semiconductor devices, semiconductor device pin, and method for the manufacturing of pins 失效用于半导体器件的壳体，半导体器件引脚和用于制造引脚的方法公开(公告)号：US07060534B2
公开(公告)日：2006-06-13
申请号：US10757549
申请日：2004-01-15
IPC分类号： H01L21/44
CPC分类号： H01L23/49582 , H01L2924/0002 , H05K3/3426 , H05K2201/10689 , H05K2201/10909 , Y02P70/613 , H01L2924/00
摘要： A housing, in particular for semiconductor devices, a semiconductor device pin, and a method for the manufacturing of pins wherein at least one pin is punched out from a basic body, in particular a lead framed, by means of one or a plurality of punching process steps, wherein the pin is coated with a separate metal layer after the final punching out of said pin.
摘要翻译： 一种用于半导体器件的壳体，半导体器件引脚和用于制造引脚的方法，其中至少一个引脚通过一个或多个冲压从基体（特别是引线框架）冲压出来 工艺步骤，其中在所述销的最后冲压之后，销被单独的金属层涂覆。
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公开(公告)号：US20050057988A1
公开(公告)日：2005-03-17
申请号：US10487255
申请日：2002-08-21
申请人： Eric Cordes , Christian Stocken , Georg Eggers , Jens Luepke
发明人： Eric Cordes , Christian Stocken , Georg Eggers , Jens Luepke
CPC分类号： G11C29/50012 , G11C7/1051 , G11C7/1087 , G11C11/401 , G11C29/50
摘要： A test method for a semiconductor memory device having a bidirectional data strobe terminal for a data strobe signal, and having at least one data terminal for a data signal at a test apparatus, which can at least generate data strobe and data signals and also transfer and evaluate data signals. The memory device is connected to a test apparatus, which generates data strobe and data signals, and transfers and evaluates data signals. In the course of the test using the data strobe and data signals, data are transferred from the first semiconductor memory device to a second semiconductor memory device of identical type and are evaluated after a read-out from the second semiconductor memory device by the test apparatus.
摘要翻译： 一种用于半导体存储器件的测试方法，具有用于数据选通信号的双向数据选通端子，并且在测试装置处具有用于数据信号的至少一个数据端，其至少可以产生数据选通和数据信号， 评估数据信号。 存储器件连接到产生数据选通和数据信号的测试装置，并传送和评估数据信号。 在使用数据选通和数据信号的测试过程中，数据从第一半导体存储器件传送到相同类型的第二半导体存储器件，并且在通过测试装置从第二半导体存储器件读出之后被评估 。
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