公开(公告)号：US07509457B2

公开(公告)日：2009-03-24

申请号：US11065537

申请日：2005-02-24

申请人： Erik Richter Altman ,  Peter George Capek ,  Michael Karl Gschwind ,  Charles Ray Johns ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  James Allan Kahle ,  Sumedh W. Sathaye ,  John-David Wellman ,  Ravi Nair

发明人： Erik Richter Altman ,  Peter George Capek ,  Michael Karl Gschwind ,  Charles Ray Johns ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  James Allan Kahle ,  Sumedh W. Sathaye ,  John-David Wellman ,  Ravi Nair

IPC分类号： G06F12/00

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。

公开(公告)号：US08091050B2

公开(公告)日：2012-01-03

申请号：US12243427

申请日：2008-10-01

申请人： Pradip Bose ,  Prabhakar N. Kudva ,  Jude A. Rivers ,  Pia N. Sanda ,  John-David Wellman

发明人： Pradip Bose ,  Prabhakar N. Kudva ,  Jude A. Rivers ,  Pia N. Sanda ,  John-David Wellman

IPC分类号： G06F17/50 ,  G06F11/22

CPC分类号： G06F17/5036 ,  G06F2217/82

摘要： Mechanisms for modeling system level effects of soft errors are provided. Mechanisms are provided for integrating device-level and component-level soft error rate (SER) analysis mechanisms with micro-architecture level performance analysis tools during a concept phase of the IC design to thereby generate a SER analysis tool. A first SER profile for the IC design is generated by applying the SER analysis tool to the IC design. At a later phase of the IC design, detailed information about SER vulnerabilities of logic and storage elements within the IC design are obtained and the first SER profile is refined based on the detailed information about SER vulnerabilities to thereby generate a second SER profile for the IC design. Modifications to the IC design are made at one or more phases of the IC design based on one of the first SER profile or the second SER profile.

摘要翻译： 提供了对软错误的系统级别影响进行建模的机制。 提供了在IC设计的概念阶段将器件级和组件级软错误率（SER）分析机制与微架构级性能分析工具集成的机制，从而生成SER分析工具。 通过将SER分析工具应用于IC设计，可以生成IC设计的第一个SER简档。 在IC设计的后期阶段，获得关于IC设计中逻辑和存储元件的SER漏洞的详细信息，并且基于关于SER漏洞的详细信息来改进第一SER简档，从而为IC生成第二SER简档 设计。 基于第一SER简档或第二SER简档中的一个，在IC设计的一个或多个阶段进行对IC设计的修改。

公开(公告)号：US20100083203A1

公开(公告)日：2010-04-01

申请号：US12243427

申请日：2008-10-01

申请人： Pradip Bose ,  Prabhakar N. Kudva ,  Jude A. Rivers ,  Pia N. Sanda ,  John-David Wellman

发明人： Pradip Bose ,  Prabhakar N. Kudva ,  Jude A. Rivers ,  Pia N. Sanda ,  John-David Wellman

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/82

摘要： Mechanisms for modeling system level effects of soft errors are provided. Mechanisms are provided for integrating device-level and component-level soft error rate (SER) analysis mechanisms with micro-architecture level performance analysis tools during a concept phase of the IC design to thereby generate a SER analysis tool. A first SER profile for the IC design is generated by applying the SER analysis tool to the IC design. At a later phase of the IC design, detailed information about SER vulnerabilities of logic and storage elements within the IC design are obtained and the first SER profile is refined based on the detailed information about SER vulnerabilities to thereby generate a second SER profile for the IC design. Modifications to the IC design are made at one or more phases of the IC design based on one of the first SER profile or the second SER profile.

摘要翻译： 提供了对软错误的系统级别影响进行建模的机制。 提供了在IC设计的概念阶段将器件级和组件级软错误率（SER）分析机制与微架构级性能分析工具集成的机制，从而生成SER分析工具。 通过将SER分析工具应用于IC设计，可以生成IC设计的第一个SER简档。 在IC设计的后期阶段，获得关于IC设计中逻辑和存储元件的SER漏洞的详细信息，并且基于关于SER漏洞的详细信息来改进第一SER简档，从而为IC生成第二SER简档 设计。 基于第一SER简档或第二SER简档中的一个，在IC设计的一个或多个阶段进行对IC设计的修改。

公开(公告)号：US06711651B1

公开(公告)日：2004-03-23

申请号：US09655642

申请日：2000-09-05

申请人： Jaime H. Moreno ,  Jude A. Rivers ,  John-David Wellman

发明人： Jaime H. Moreno ,  Jude A. Rivers ,  John-David Wellman

IPC分类号： G06F1300

CPC分类号： G06F12/0862 ,  G06F12/0815 ,  G06F2212/6024

摘要： A method and apparatus are provided for moving at least one of instructions and operand data throughout a plurality of caches included in a multiprocessor computer system, wherein each of the plurality of caches is included in one of a plurality of processing nodes of the system so as to provide history-based movement of shared-data in coherent cache memories. A plurality of entries are stored in a consume after produce (CAP) table attached to each of the plurality of caches. Each of the entries is associated with a plurality of storage elements in one of the plurality of caches and includes information of prior usage of the plurality of storage elements by each of the plurality of processing nodes. Upon a miss by a processing node to a cache included therein, any storage elements that caused the miss are transferred to the cache from one of main memory and another cache. An entry is created in the table that is associated with the storage elements that caused the miss. A push prefetching engine may be used to create the entry.

摘要翻译： 提供了一种方法和装置，用于在包括在多处理器计算机系统中的多个高速缓存中移动指令和操作数数据中的至少一个，其中多个高速缓存中的每一个包括在系统的多个处理节点之一中，以便 以共享缓存存储器中的共享数据提供基于历史的移动。 在附加到多个高速缓存中的每一个的产生（CAP）表之后，将多个条目存储在消费中。 每个条目与多个高速缓存之一中的多个存储元件相关联，并且包括多个处理节点中的每一个的多个存储元件的先前使用的信息。 当处理节点错过其中包含的高速缓存时，导致未命中的任何存储元件从主存储器和另一高速缓存之一传送到高速缓存。 在表中创建一个与导致未命中的存储元素相关联的条目。 推式预取引擎可用于创建条目。

公开(公告)号：US07130963B2

公开(公告)日：2006-10-31

申请号：US10620734

申请日：2003-07-16

申请人： Sameh W. Asaad ,  Jaime H. Moreno ,  Jude A. Rivers ,  John-David Wellman

发明人： Sameh W. Asaad ,  Jaime H. Moreno ,  Jude A. Rivers ,  John-David Wellman

IPC分类号： G06F12/00

CPC分类号： G06F9/381

摘要： A system for instruction memory storage and processing in a computing device having a processor, the system is based on backwards branch control information and comprises a dynamic loop buffer (DLB) which is a tagless array of data organized as a direct-mapped structure; a DLB controller having a primary memory unit partitioned into a plurality of banks for controlling the state of the instruction memory system and accepting a program counter address as an input, the DLB controller outputs distinct signals. The system further comprises an address register located in the memory of the computing device, it is a staging register for the program counter address and an instruction fetch process that takes two cycles of the processor clock; and a bank select unit for serving as a program counter address decoder to accept the program counter address and to output a bank enable signal for selecting a bank in a primary memory unit, and a decoded address for access within the selected bank.

摘要翻译： 一种用于具有处理器的计算设备中的指令存储器存储和处理的系统，所述系统基于向后分支控制信息，并且包括动态循环缓冲器（DLB），其是被组织为直接映射结构的无标记数据阵列; DLB控制器具有划分为多​​个存储体的主存储器单元，用于控制指令存储器系统的状态并接受程序计数器地址作为输入，DLB控制器输出不同的信号。 该系统还包括位于计算设备的存储器中的地址寄存器，它是用于程序计数器地址的分段寄存器和执行处理器时钟的两个周期的指令获取处理; 以及用于作为程序计数器地址解码器接受程序计数器地址并输出用于选择主存储器单元中的存储体的存储体使能信号的存储体选择单元和在所选择的存储体内的存取的解码地址。

公开(公告)号：US07496733B2

公开(公告)日：2009-02-24

申请号：US11924977

申请日：2007-10-26

申请人： Erik Altman ,  Michael Karl Gschwind ,  Jude A. Rivers ,  Sumedh Wasudeo Sathaye ,  John-David Wellman ,  Victor Zyuban

发明人： Erik Altman ,  Michael Karl Gschwind ,  Jude A. Rivers ,  Sumedh Wasudeo Sathaye ,  John-David Wellman ,  Victor Zyuban

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867 ,  G06F9/3885

摘要： A pipeline system and method includes a plurality of operational stages. The stages include a pointer register stage which stores pointer information and updates, and a rename and dependence checking stage located downstream of the pointer register stage, which renames registers and determines if dependencies exist. A functional unit provides pointer information updates to the pointer register stage such that pointer information is processed and updated to the pointer register stage before or in parallel with the register dependency checking.

摘要翻译： 管道系统和方法包括多个操作阶段。 这些阶段包括存储指针信息和更新的指针寄存器阶段，以及位于指针寄存器阶段下游的重命名和依赖性检查阶段，其重新命名寄存器并确定是否存在相关性。 功能单元向指针寄存器阶段提供指针信息更新，使得指针信息在寄存器依赖性检查之前或与寄存器依赖性检查并行地更新到指针寄存器阶段。

公开(公告)号：US07325124B2

公开(公告)日：2008-01-29

申请号：US10828794

申请日：2004-04-21

申请人： Erik Altman ,  Michael Karl Gschwind ,  Jude A. Rivers ,  Sumedh Wasudeo Sathaye ,  John-David Wellman ,  Victor Zyuban

发明人： Erik Altman ,  Michael Karl Gschwind ,  Jude A. Rivers ,  Sumedh Wasudeo Sathaye ,  John-David Wellman ,  Victor Zyuban

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867 ,  G06F9/3885

摘要： A pipeline system and method includes a plurality of operational stages. The stages include a pointer register stage which stores pointer information and updates, and a rename and dependence checking stage located downstream of the pointer register stage, which renames registers and determines if dependencies exist. A functional unit provides pointer information updates to the pointer register stage such that pointer information is processed and updated to the pointer register stage before or in parallel with the register dependency checking.

摘要翻译： 管道系统和方法包括多个操作阶段。 这些阶段包括存储指针信息和更新的指针寄存器阶段，以及位于指针寄存器阶段下游的重命名和依赖性检查阶段，其重新命名寄存器并确定是否存在相关性。 功能单元向指针寄存器阶段提供指针信息更新，使得指针信息在寄存器依赖性检查之前或与寄存器依赖性检查并行地更新到指针寄存器阶段。

公开(公告)号：US06678795B1

公开(公告)日：2004-01-13

申请号：US09639263

申请日：2000-08-15

申请人： Jaime H. Moreno ,  Jude A. Rivers ,  John-David Wellman

发明人： Jaime H. Moreno ,  Jude A. Rivers ,  John-David Wellman

IPC分类号： G06F1208

CPC分类号： G06F12/0862 ,  G06F2212/6024

摘要： There is provided a method for fetching at least one of instructions and operand data from a second memory into a first memory of a computer system having at least one processor. The method includes the step of storing a plurality of entries in a table associated with the first memory. Each entry is associated with a memory page that includes a plurality of storage elements in the second memory, and includes information of prior access by the at least one processor to each of the plurality of storage elements. Upon a miss to the first memory from the at least one processor based upon a request, the table is searched for a given entry associated with a given page that includes a target of the request. If the given entry is found, then at least one prefetch request is generated to fetch at least one storage element included in the given page from the second memory to the first memory, based upon given information comprised in the given entry.

摘要翻译： 提供了一种用于将指令和操作数中的至少一个从第二存储器读取到具有至少一个处理器的计算机系统的第一存储器中的方法。 该方法包括将多个条目存储在与第一存储器相关联的表中的步骤。 每个条目与包括第二存储器中的多个存储元件的存储器页面相关联，并且包括至少一个处理器对多个存储元件中的每一个的先前访问的信息。 在基于请求错过从至少一个处理器到第一存储器时，搜索与包括请求的目标的给定页面相关联的给定条目的表。 如果找到给定条目，则基于给定条目中包含的给定信息，生成至少一个预取请求以从包含在给定页面中的至少一个存储元件从第二存储器提取到第一存储器。

公开(公告)号：US06907477B2

公开(公告)日：2005-06-14

申请号：US10782044

申请日：2004-02-19

申请人： Erik R. Altman ,  Peter G. Capek ,  Michael Gschwind ,  Harm Peter Hofstee ,  James Allan Kahle ,  Ravi Nair ,  Sumedh Wasudeo Sathaye ,  John-David Wellman

发明人： Erik R. Altman ,  Peter G. Capek ,  Michael Gschwind ,  Harm Peter Hofstee ,  James Allan Kahle ,  Ravi Nair ,  Sumedh Wasudeo Sathaye ,  John-David Wellman

IPC分类号： G06F12/10 ,  G06F13/28 ,  G06F9/28 ,  G06F13/368

CPC分类号： G06F12/1027 ,  G06F2212/682

摘要： A method and system for attached processing units accessing a shared memory in an SMT system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

摘要翻译： 一种用于附接处理单元访问SMT系统中的共享存储器的方法和系统。 在一个实施例中，系统包括共享存储器。 该系统还包括耦合到共享存储器的多个处理元件。 多个处理单元中的每一个包括处理单元，直接存储器存取控制器和多个附加的处理单元。 每个直接存储器访问控制器包括地址转换机制，从而使得每个相关联的附属处理单元能够以无限制的方式访问共享存储器，而无需地址转换机制。 每个附加的处理单元被配置为向相关联的直接存储器访问控制器发出请求以访问指定要作为虚拟地址访问的地址范围的共享存储器。 相关联的直接存储器访问控制器被配置为将虚拟地址的范围转换为相关的物理地址范围。

公开(公告)号：US06779049B2

公开(公告)日：2004-08-17

申请号：US09736585

申请日：2000-12-14

申请人： Erik R. Altman ,  Peter G. Capek ,  Michael Gschwind ,  Harm Peter Hofstee ,  James Allan Kahle ,  Ravi Nair ,  Sumedh Wasudeo Sathaye ,  John-David Wellman ,  Masakazu Suzuoki ,  Takeshi Yamazaki

发明人： Erik R. Altman ,  Peter G. Capek ,  Michael Gschwind ,  Harm Peter Hofstee ,  James Allan Kahle ,  Ravi Nair ,  Sumedh Wasudeo Sathaye ,  John-David Wellman ,  Masakazu Suzuoki ,  Takeshi Yamazaki

IPC分类号： G06F1328

CPC分类号： G06F12/1027 ,  G06F2212/682

摘要： A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

摘要翻译： 用于在SMP系统中访问共享存储器的附加处理单元的方法和系统。 在一个实施例中，系统包括共享存储器。 该系统还包括耦合到共享存储器的多个处理元件。 多个处理单元中的每一个包括处理单元，直接存储器存取控制器和多个附加的处理单元。 每个直接存储器访问控制器包括地址转换机制，从而使得每个相关联的附属处理单元能够以无限制的方式访问共享存储器，而无需地址转换机制。 每个附加的处理单元被配置为向相关联的直接存储器访问控制器发出请求以访问指定要作为虚拟地址访问的地址范围的共享存储器。 相关联的直接存储器访问控制器被配置为将虚拟地址的范围转换为相关的物理地址范围。