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11.发明申请公开(公告)号：US20170148980A1
公开(公告)日：2017-05-25
申请号：US15396700
申请日：2017-01-02
Applicant: Everspin Technologies, Inc.
Inventor： Sanjeev Aggarwal , Kerry Nagel , Jason Janesky
CPC classification number: H01L43/12 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/10
Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes.
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12.发明授权Magnetoresistive structure having two dielectric layers, and method of manufacturing same 有权具有两个电介质层的磁阻结构及其制造方法公开(公告)号：US09548442B2
公开(公告)日：2017-01-17
申请号：US14797172
申请日：2015-07-12
Applicant: Everspin Technologies, Inc.
Inventor： Sanjeev Aggarwal , Kerry Nagel , Jason Janesky
CPC classification number: H01L43/12 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/10
Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least an encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes.
Abstract translation: 具有两个电介质层的磁阻结构及其制造方法包括位于两个电介质层之间的自由磁性层。 制造方法包括至少两个蚀刻工艺和至少一个介于其间的封装工艺，其中在蚀刻工艺之间形成在部分形成的磁阻堆叠的侧壁上的封装。
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公开(公告)号：US20140190933A1
公开(公告)日：2014-07-10
申请号：US13826658
申请日：2013-03-14
Applicant: Everspin Technologies, Inc.
Inventor： Sarin Deshpande , Sanjeev Aggarwal , Kerry Nagel
IPC: G11B5/127
CPC classification number: G11B5/127 , G11C11/161 , H01L43/12 , Y10T29/49052
Abstract: A method of manufacturing a magnetoresistive-based device includes a metal hard mask that is inert to a top electrode etch chemistry and that has low sputter yield during a magnetic stack sputter. The metal hard mask is patterned by the photo resist and the photo mask is then stripped and the top electrode (overlying magnetic materials of the magnetoresistive-based device) is patterned by the metal hard mask.
Abstract translation: 制造基于磁阻的器件的方法包括对顶部电极蚀刻化学物质是惰性的并且在磁堆栈溅射期间具有低的溅射产率的金属硬掩模。 金属硬掩模由光致抗蚀剂构图，然后剥离光掩模，并且通过金属硬掩模对顶部电极（基于磁阻的装置的覆盖磁性材料）进行图案化。
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14.发明授权公开(公告)号：US11925122B2
公开(公告)日：2024-03-05
申请号：US17468896
申请日：2021-09-08
Applicant: Everspin Technologies, Inc.
Inventor： Sanjeev Aggarwal , Kerry Nagel , Jason Janesky
CPC classification number: H10N50/01 , G11C11/161 , H10N50/10 , H10N50/80 , H10N50/85
Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.
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Patent Agency Ranking
公开(公告)号：US11264564B2
公开(公告)日：2022-03-01
申请号：US16783740
申请日：2020-02-06
Applicant: Everspin Technologies, Inc.
Inventor： Sumio Ikegawa , Hamid Almasi , Shimon , Kerry Nagel , Han Kyu Lee
Abstract: A magnetoresistive device may include one or more electrodes or electrically conductive lines and a fixed region and a free region disposed between the electrodes or electrically conductive lines. The fixed region may have a fixed magnetic state and the free region may be configured to have a first magnetic state and a second magnetic state. The free region may store a first value when in the first magnetic state and store a second value when in the second magnetic state. The magnetoresistive device may further include a dielectric layer between the free region and the fixed region and a spin-Hall (SH) material proximate to at least a portion of the free region. An insertion layer may be disposed between the SH material and the free region.
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16.发明申请公开(公告)号：US20180123032A1
公开(公告)日：2018-05-03
申请号：US15856202
申请日：2017-12-28
Applicant: Everspin Technologies, Inc.
Inventor： Sanjeev Aggarwal , Kerry Nagel , Jason Janesky
CPC classification number: H01L43/12 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/10
Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.
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17.发明申请Magnetoresistive Structure having Two Dielectric Layers, and Method of Manufacturing Same 审中-公开具有两个介电层的磁阻结构及其制造方法公开(公告)号：US20150318465A1
公开(公告)日：2015-11-05
申请号：US14797172
申请日：2015-07-12
Applicant: Everspin Technologies, Inc.
Inventor： Sanjeev Aggarwal , Kerry Nagel , Jason Janesky
CPC classification number: H01L43/12 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/10
Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least an encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes.
Abstract translation: 具有两个电介质层的磁阻结构及其制造方法包括位于两个电介质层之间的自由磁性层。 制造方法包括至少两个蚀刻工艺和至少一个介于其间的封装工艺，其中在蚀刻工艺之间形成在部分形成的磁阻堆叠的侧壁上的封装。
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公开(公告)号：US20150079699A1
公开(公告)日：2015-03-19
申请号：US14532797
申请日：2014-11-04
Applicant: Everspin Technologies, Inc.
Inventor： Sarin Deshpande , Sanjeev Aggarwal , Kerry Nagel
IPC: H01L43/12
CPC classification number: G11B5/127 , G11C11/161 , H01L43/12 , Y10T29/49052
Abstract: A method of manufacturing a magnetoresistive-based device includes a metal hard mask that is inert to a top electrode etch chemistry and that has low sputter yield during a magnetic stack sputter. The metal hard mask is patterned by the photo resist and the photo mask is then stripped and the top electrode (overlying magnetic materials of the magnetoresistive-based device) is patterned by the metal hard mask.
Abstract translation: 制造基于磁阻的器件的方法包括对顶部电极蚀刻化学物质是惰性的并且在磁堆栈溅射期间具有低的溅射产率的金属硬掩模。 金属硬掩模由光致抗蚀剂构图，然后剥离光掩模，并且通过金属硬掩模对顶部电极（基于磁阻的装置的覆盖磁性材料）进行图案化。
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19.发明申请公开(公告)号：US20140287536A1
公开(公告)日：2014-09-25
申请号：US14283413
申请日：2014-05-21
Applicant: Everspin Technologies, Inc.
Inventor： Kerry Nagel , Sarin Deshpande , Moazzem Hossain , Sanjeev Aggarwal
IPC: H01L43/12 , H01L21/768
CPC classification number: H01L43/12 , H01L21/76883 , H01L21/76898 , H01L23/544 , H01L27/222 , H01L2223/54426 , H01L2924/0002 , H01L2924/00
Abstract: A method is provided for forming a first via with an electrically conductive material, for example, copper, that is formed over and coupled to a conductive landing pad of an MRAM array. A sputter step is performed to lower the surface of the first via below that of a surrounding dielectric material. This recess is repeated in subsequent processing steps, providing alignment marks for the formation of a magnetic tunnel junction. The magnetic tunnel junction may be offset from the first via, and a second via being formed above the magnetic tunnel junction and to a conductive layer.
Abstract translation: 提供了一种用于形成第一通孔的方法，其中导电材料例如铜形成在MRAM阵列的导电着陆焊盘上并耦合到MRAM阵列的导电着陆焊盘。 执行溅射步骤以将第一通孔的表面降低到低于周围电介质材料的表面。 在随后的处理步骤中重复该凹槽，提供用于形成磁性隧道结的对准标记。 磁性隧道结可以偏离第一通孔，并且第二通孔形成在磁性隧道结上方和导电层上。
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