Abstract:
Embodiments of phase-generation circuitry and methods for generating a multiphase signal with duty-cycle correction are generally described herein. The phase-generation circuitry may include a plurality of controllable delay stages arranged in series and phase detector circuitry. Each delay stage may be configured to phase shift a differential signal based on a control signal. The phase detector circuitry may be configured to generate the control signal based on a first time difference and a second time difference. The first time difference may be a time difference between rising edges of a first component of the differential signal and a second component of a phase-shifted signal. The second time difference may be a time difference between falling edges of the first component of the differential signal and the second component of the phase-shifted signal. Other circuits, systems, and methods are described.
Abstract:
Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between a clock signal and a reference clock signal, and a charge pump that receives the detected phase difference. A low pass filter may filter an output from the charge pump. The delay locked loop may further include a delay line having a plurality of delay elements, the plurality of delay elements including a first selectable group and a second selectable group that is larger than the first selectable group. A first clock signal from the first group of delay elements may be provided to the phase detector to first synchronize the delay locked loop, and following the synchronization, a second clock signal from the second group may be employed to synchronize the delay locked loop.
Abstract:
Some embodiments include apparatus and methods having a clock path with a combination of current-mode logic (CML) based and complementary metal-oxide semiconductor (CMOS) components.
Abstract:
An apparatus, system and method for adaptively controlling a frame interval between ultrasound scanning frames of an ultrasound elasticity imaging scan. The system includes a transmitter for transmitting ultrasound beams to a subject during an ultrasound elasticity imaging scan, and a receiver for receiving ultrasound beam echoes from the subject responsive to transmitted ultrasound beams. The system also includes a processor for processing a plurality of the ultrasound beam echoes to determine a strain variation of the tissue undergoing strain, calculating a value for an ultrasound scanning frame interval adapted for imaging the tissue undergoing the determined strain variation, and setting the value of the ultrasound scanning frame interval for acquiring ultrasound elasticity images of the tissue undergoing the determined strain variation.
Abstract:
A power supply system includes a power converter, a switch, and a controller. The power converter is operable for providing power to a load. The switch is coupled to the power converter and is operable for adjusting the power to the load. The switch has a gate, a source and a drain. The controller is coupled to the switch and is operable for controlling a state of the switch. The controller has a first control terminal for providing a gate voltage to the gate of the switch, a second control terminal for providing a source voltage to the source of the switch, and an input terminal for receiving a supply voltage via the source of the switch. The controller is also operable for limiting the supply voltage within a predetermined maximum level by regulating the gate voltage to a preset level.
Abstract:
An apparatus, system and method for adaptively controlling a frame interval between ultrasound scanning frames of an ultrasound elasticity imaging scan. The system includes a transmitter for transmitting ultrasound beams to a subject during an ultrasound elasticity imaging scan, and a receiver for receiving ultrasound beam echoes from the subject responsive to transmitted ultrasound beams. The system also includes a processor for processing a plurality of the ultrasound beam echoes to determine a strain variation of the tissue undergoing strain, calculating a value for an ultrasound scanning frame interval adapted for imaging the tissue undergoing the determined strain variation, and setting the value of the ultrasound scanning frame interval for acquiring ultrasound elasticity images of the tissue undergoing the determined strain variation.
Abstract:
Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for correcting duty-cycle distortion of differential output clock signals provided from a clock distribution network. In one such method, a single-ended clock signal is generated from differential input clock signals for distribution over a clock distribution network and from which the differential output clock signals are generated. A delay of a model delay path is matched to a propagation delay of the clock distribution network, and the single ended clock signal is adjusted to compensate for duty-cycle distortion.
Abstract:
There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original clock signal, with the original clock signal and to select a signal based on the proximity of the phase characteristic of the three signals to the original signal. The selection of a clock signal that most closely approximates the original significantly reduces lock time when attempting to synchronize an internal clock with an external clock. Additionally, there is provided a method for comparing three clock signals with an original clock signal and selecting from the three clock signals one that is approximately in phase with the original clock signal.
Abstract:
A network printer for users printing documents in the Internet contains a keypad, when a user on the keypad enters a number, the printer sends the number to a first server; the first Internet server translates the number into the URL of a document in a second server in the Internet, and sends the URL to the printer; according to the URL, the printer retrieves the document from the second server via Internet, and prints the document.
Abstract:
A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes a voltage-controlled delay line generating a plurality of delayed clock signals having different phases. A plurality of the delayed clock signals are combined to generate a plurality of output signals. During an initialization period, an initialization circuit sets the delay of the delay line to a minimum delay value and then compares this delay value to the period of the input clock signal. Based on this comparison, the initialization circuit programs the programmable divider and adjusts the number of delayed clock signals combined to generate the output signals. More specifically, as the frequency of the reference clock signal increases, the divider is programmed to divide by a greater number, and a larger number of delay clock signals are combined to generate the output signals.