公开(公告)号：US20110121406A1

公开(公告)日：2011-05-26

申请号：US12871655

申请日：2010-08-30

申请人： Tsung-Lin Lee ,  Chih Cheih Yeh ,  Chang-Yun Chang ,  Feng Yuan

发明人： Tsung-Lin Lee ,  Chih Cheih Yeh ,  Chang-Yun Chang ,  Feng Yuan

IPC分类号： H01L27/088 ,  H01L21/28

CPC分类号： H01L21/823431 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.

摘要翻译： 集成电路结构包括包括第一器件区域中的第一部分和第二器件区域中的第二部分的半导体衬底。 第一半导体鳍片在半导体衬底之上并且具有第一鳍片高度。 第二半导体鳍片在半导体衬底之上并且具有第二鳍片高度。 第一鳍高度大于第二翅片高度。

公开(公告)号：US20120100673A1

公开(公告)日：2012-04-26

申请号：US13343586

申请日：2012-01-04

申请人： Ming-Feng Shieh ,  Tsung-Lin Lee ,  Chang-Yun Chang

发明人： Ming-Feng Shieh ,  Tsung-Lin Lee ,  Chang-Yun Chang

IPC分类号： H01L21/336

CPC分类号： H01L21/823431 ,  H01L21/845

摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer having a plurality of mask strips over the semiconductor substrate and over the active region; forming a third mask layer over the second mask layer, wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and performing a second etch to the semiconductor substrate through the opening.

摘要翻译： 形成集成电路结构的方法包括提供半导体衬底; 提供第一光刻掩模，第二光刻掩模和第三光刻掩模; 在所述半导体衬底上形成第一掩模层，其中使用所述第一光刻掩模限定所述第一掩模层的图案; 对所述半导体衬底执行第一蚀刻以使用所述第一掩模层限定有源区; 在所述半导体衬底上并在所述有源区上形成具有多个掩模条的第二掩模层; 在所述第二掩模层上形成第三掩模层，其中所述多个掩模条的中间部分通过所述第三掩模层中的开口露出，并且所述多个掩模条的端部被所述第三掩模层覆盖; 以及通过所述开口对所述半导体衬底进行第二蚀刻。

公开(公告)号：US07511988B2

公开(公告)日：2009-03-31

申请号：US11483819

申请日：2006-07-10

申请人： Wesley Lin ,  Fang-Shi Jordan Lai ,  Chia-Fu Lee ,  Sheng Chi Lin ,  Ping-Wei Wang ,  Chang-Yun Chang ,  Tang-Xuan Zhong ,  Tsung-Lin Lee

发明人： Wesley Lin ,  Fang-Shi Jordan Lai ,  Chia-Fu Lee ,  Sheng Chi Lin ,  Ping-Wei Wang ,  Chang-Yun Chang ,  Tang-Xuan Zhong ,  Tsung-Lin Lee

IPC分类号： G11C11/41 ,  G11C7/02 ,  G11C7/24

CPC分类号： G11C11/4125

摘要： A static random access memory (SRAM) cell includes a first load device, a first pull-down transistor, and a switch-box coupled between the first load device and the first pull-down transistor. The switch-box is configured to receive a switch control signal to turn off a first connection between the first load device and the first pull-down transistor during read operations of the SRAM cell and to turn on the first connection during write operations.

摘要翻译： 静态随机存取存储器（SRAM）单元包括耦合在第一负载器件和第一下拉晶体管之间的第一负载器件，第一下拉晶体管和开关盒。 开关盒被配置为在SRAM单元的读取操作期间接收开关控制信号以关闭第一负载装置和第一下拉晶体管之间的第一连接，并且在写入操作期间接通第一连接。

公开(公告)号：US08796156B2

公开(公告)日：2014-08-05

申请号：US13343586

申请日：2012-01-04

申请人： Ming-Feng Shieh ,  Tsung-Lin Lee ,  Chang-Yun Chang

发明人： Ming-Feng Shieh ,  Tsung-Lin Lee ,  Chang-Yun Chang

IPC分类号： H01L21/302

CPC分类号： H01L21/823431 ,  H01L21/845

摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer having a plurality of mask strips over the semiconductor substrate and over the active region; forming a third mask layer over the second mask layer, wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and performing a second etch to the semiconductor substrate through the opening.

摘要翻译： 形成集成电路结构的方法包括提供半导体衬底; 提供第一光刻掩模，第二光刻掩模和第三光刻掩模; 在所述半导体衬底上形成第一掩模层，其中使用所述第一光刻掩模限定所述第一掩模层的图案; 对所述半导体衬底执行第一蚀刻以使用所述第一掩模层限定有源区; 在所述半导体衬底上并在所述有源区上形成具有多个掩模条的第二掩模层; 在所述第二掩模层上形成第三掩模层，其中所述多个掩模条的中间部分通过所述第三掩模层中的开口露出，并且所述多个掩模条的端部被所述第三掩模层覆盖; 以及通过所述开口对所述半导体衬底进行第二蚀刻。

公开(公告)号：US08110466B2

公开(公告)日：2012-02-07

申请号：US12843728

申请日：2010-07-26

申请人： Ming-Feng Shieh ,  Tsung-Lin Lee ,  Chang-Yun Chang

发明人： Ming-Feng Shieh ,  Tsung-Lin Lee ,  Chang-Yun Chang

IPC分类号： H01L21/428

CPC分类号： H01L21/823431 ,  H01L21/845

摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer having a plurality of mask strips over the semiconductor substrate and over the active region; forming a third mask layer over the second mask layer, wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and performing a second etch to the semiconductor substrate through the opening.

摘要翻译： 形成集成电路结构的方法包括提供半导体衬底; 提供第一光刻掩模，第二光刻掩模和第三光刻掩模; 在所述半导体衬底上形成第一掩模层，其中使用所述第一光刻掩模限定所述第一掩模层的图案; 对所述半导体衬底执行第一蚀刻以使用所述第一掩模层限定有源区; 在所述半导体衬底上并在所述有源区上形成具有多个掩模条的第二掩模层; 在所述第二掩模层上形成第三掩模层，其中所述多个掩模条的中间部分通过所述第三掩模层中的开口露出，并且所述多个掩模条的端部被所述第三掩模层覆盖; 以及通过所述开口对所述半导体衬底进行第二蚀刻。

公开(公告)号：US20110097863A1

公开(公告)日：2011-04-28

申请号：US12843728

申请日：2010-07-26

申请人： Ming-Feng Shieh ,  Tsung-Lin Lee ,  Chang-Yun Chang

发明人： Ming-Feng Shieh ,  Tsung-Lin Lee ,  Chang-Yun Chang

IPC分类号： H01L21/336

CPC分类号： H01L21/823431 ,  H01L21/845

摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer having a plurality of mask strips over the semiconductor substrate and over the active region; forming a third mask layer over the second mask layer, wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and performing a second etch to the semiconductor substrate through the opening.

摘要翻译： 形成集成电路结构的方法包括提供半导体衬底; 提供第一光刻掩模，第二光刻掩模和第三光刻掩模; 在所述半导体衬底上形成第一掩模层，其中使用所述第一光刻掩模限定所述第一掩模层的图案; 对所述半导体衬底执行第一蚀刻以使用所述第一掩模层限定有源区; 在所述半导体衬底上并在所述有源区上形成具有多个掩模条的第二掩模层; 在所述第二掩模层上形成第三掩模层，其中所述多个掩模条的中间部分通过所述第三掩模层中的开口露出，并且所述多个掩模条的端部被所述第三掩模层覆盖; 以及通过所述开口对所述半导体衬底进行第二蚀刻。

公开(公告)号：US20070268747A1

公开(公告)日：2007-11-22

申请号：US11483819

申请日：2006-07-10

申请人： Wesley Lin ,  Fang-Shi Jordan Lai ,  Chia-Fu Lee ,  Sheng Chi Lin ,  Ping-Wei Wang ,  Chang-Yun Chang ,  Tang-Xuan Zhong ,  Tsung-Lin Lee

发明人： Wesley Lin ,  Fang-Shi Jordan Lai ,  Chia-Fu Lee ,  Sheng Chi Lin ,  Ping-Wei Wang ,  Chang-Yun Chang ,  Tang-Xuan Zhong ,  Tsung-Lin Lee

IPC分类号： G11C11/34

CPC分类号： G11C11/4125

摘要： A static random access memory (SRAM) cell includes a first load device, a first pull-down transistor, and a switch-box coupled between the first load device and the first pull-down transistor. The switch-box is configured to receive a switch control signal to turn off a first connection between the first load device and the first pull-down transistor during read operations of the SRAM cell and to turn on the first connection during write operations.

摘要翻译： 静态随机存取存储器（SRAM）单元包括耦合在第一负载器件和第一下拉晶体管之间的第一负载器件，第一下拉晶体管和开关盒。 开关盒被配置为在SRAM单元的读取操作期间接收开关控制信号以关闭第一负载装置和第一下拉晶体管之间的第一连接，并且在写入操作期间接通第一连接。

公开(公告)号：US20110089526A1

公开(公告)日：2011-04-21

申请号：US12838264

申请日：2010-07-16

申请人： Tsung-Lin Lee ,  Chang-Yun Chang

发明人： Tsung-Lin Lee ,  Chang-Yun Chang

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/762 ,  H01L21/76232

摘要： A system and method for forming multi recessed shallow trench isolation structures on substrate of an integrated circuit is provided. An integrated circuit includes a substrate, at least two shallow trench isolation (STI) structures formed in the substrate, an oxide fill disposed in the at least two STI structures, and semiconductor devices disposed on the oxide fill in the at least two STI structures. A first STI structure is formed to a first depth and a second STI structure is formed to a second depth. The oxide fill fills the at least two STI structures, and the first depth and the second depth are based on semiconductor device characteristics of semiconductor devices disposed thereon.

摘要翻译： 提供了一种用于在集成电路的衬底上形成多凹槽浅沟槽隔离结构的系统和方法。 集成电路包括衬底，在衬底中形成的至少两个浅沟槽隔离（STI）结构，设置在至少两个STI结构中的氧化物填充物，以及设置在至少两个STI结构中的氧化物填充物上的半导体器件。 第一STI结构形成为第一深度，并且第二STI结构形成为第二深度。 氧化物填充物填充至少两个STI结构，并且第一深度和第二深度基于设置在其上的半导体器件的半导体器件特性。

公开(公告)号：US20080296702A1

公开(公告)日：2008-12-04

申请号：US11807652

申请日：2007-05-30

申请人： Tsung-Lin Lee ,  Chang-Yun Chang ,  Sheng-Da Liu ,  Fu-Liang Yang

发明人： Tsung-Lin Lee ,  Chang-Yun Chang ,  Sheng-Da Liu ,  Fu-Liang Yang

IPC分类号： H01L29/76

CPC分类号： H01L21/823437 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/088 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor structure includes a semiconductor substrate; and a first Fin field-effect transistor (FinFET) and a second FinFET at a surface of the semiconductor substrate. The first FinFET includes a first fin; and a first gate electrode over a top surface and sidewalls of the first fin. The second FinFET includes a second fin spaced apart from the first fin by a fin space; and a second gate electrode over a top surface and sidewalls of the second fin. The second gate electrode is electrically disconnected from the first gate electrode. The first and the second gate electrodes have a gate height greater than about one half of the fin space.

摘要翻译： 半导体结构包括半导体衬底; 以及在半导体衬底的表面处的第一Fin场效应晶体管（FinFET）和第二FinFET。 第一个FinFET包括第一个鳍; 以及在第一鳍的顶表面和侧壁上的第一栅电极。 第二FinFET包括通过鳍片空间与第一鳍片间隔开的第二鳍片; 以及在第二鳍的顶表面和侧壁上的第二栅电极。 第二栅电极与第一栅电极电断开。 第一和第二栅电极具有大于翅片空间的约一半的栅极高度。

公开(公告)号：US08482073B2

公开(公告)日：2013-07-09

申请号：US12731411

申请日：2010-03-25

申请人： Hung-Ming Chen ,  Shao-Ming Yu ,  Chang-Yun Chang

发明人： Hung-Ming Chen ,  Shao-Ming Yu ,  Chang-Yun Chang

IPC分类号： H01L29/06 ,  H01L29/16 ,  H01L29/772

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L29/7848 ,  H01L29/785

摘要： An integrated circuit including a plurality of Fin field effect transistors (FINFETs) is provided. The integrated circuit includes a plurality of fin-channel bodies over a substrate. The fin-channel bodies include a first fin-channel body and a second fin-channel body. A gate structure is disposed over the fin-channel bodies. At least one first source/drain (S/D) region of a first FINFET is adjacent the first fin-channel body. At least one second source/drain (S/D) region of a second FINFET is adjacent the second fin-channel body. The at least one first S/D region is electrically coupled with the at least one second S/D region. The at least one first and second S/D regions are substantially free from including any fin structure.

摘要翻译： 提供了包括多个Fin场效应晶体管（FINFET）的集成电路。 集成电路包括在衬底上的多个鳍状通道体。 鳍状通道体包括第一鳍状物通道体和第二鳍状物通道体。 栅极结构设置在翅片通道体上。 第一FINFET的至少一个第一源极/漏极（S / D）区域与第一鳍片通道主体相邻。 第二FINFET的至少一个第二源极/漏极（S / D）区域与第二鳍片通道主体相邻。 所述至少一个第一S / D区域与所述至少一个第二S / D区域电耦合。 至少一个第一和第二S / D区域基本上不包括任何翅片结构。