公开(公告)号：US4375087A

公开(公告)日：1983-02-22

申请号：US138806

申请日：1980-04-09

Applicant: Frank M. Wanlass

Inventor： Frank M. Wanlass

IPC: G11C17/00 ,  G11C14/00 ,  G11C16/04 ,  H01L23/522 ,  H01L29/10 ,  H01L29/788 ,  G11C13/00 ,  G11C11/44

CPC classification number: H01L23/522 ,  G11C16/0425 ,  H01L29/1087 ,  H01L29/7883 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/901

Abstract: A floating gate tunneling metal oxide semiconductor (FATMOS) transistor is formed in a well region on a semiconductive substrate of a conductivity type opposite to that of the well region, so that charging and discharging of the FATMOS floating gate is accomplished by controlling the potential of the well region. As a result, in an electrically erasable programmable read-only memory, each memory cell requires only one FATMOS transistor, the need for an additional control transistor having been eliminated. Selection of individual memory cells is enhanced by providing a floating gate which only partially overlies the FATMOS transistor channel, so that the overlying FATMOS control electrode performs an "and" gate function independently of the floating gate.

Abstract translation: 在与阱区相反的导电类型的半导体衬底上的阱区中形成浮栅隧穿金属氧化物半导体（FATMOS）晶体管，从而通过控制FATMOS浮栅的充电和放电来实现 井区。 结果，在电可擦除可编程只读存储器中，每个存储器单元仅需要一个FATMOS晶体管，已经消除了对另外的控制晶体管的需要。 通过提供仅部分覆盖FATMOS晶体管沟道的浮动栅极来增强单独存储单元的选择，使得上覆的FATMOS控制电极独立于浮置栅极执行“和”栅极功能。

公开(公告)号：US4203159A

公开(公告)日：1980-05-13

申请号：US948683

申请日：1978-10-05

Applicant: Frank M. Wanlass

Inventor： Frank M. Wanlass

IPC: G11C11/402 ,  G11C7/00 ,  G11C11/24

CPC classification number: G11C11/402 ,  G11C11/4023

Abstract: An electronic memory is described which has only two transistors in each memory cell, but does not require that data processing be periodically interrupted to enable refreshing. It adds to a typical, single transistor cell dynamic memory one additional transistor per cell, and a duplication of the driving and sensing circuitry typically included in such a memory. The additional transistor in each cell provides access to the same for refreshing, which refreshing is accomplished by the additional driving and sensing circuitry at the very same time the memory is otherwise being accessed for data processing.

Abstract translation: 描述了在每个存储器单元中仅具有两个晶体管的电子存储器，但不要求周期性地中断数据处理以实现刷新。 它增加了典型的单晶体管单元动态存储器，每个单元一个附加晶体管，以及通常包括在这种存储器中的驱动和感测电路的复制。 每个单元中的附加晶体管提供对其的访问以进行刷新，该刷新在附加的驱动和感测电路实现的同时，存储器另外被存取用于数据处理。

公开(公告)号：US06069047A

公开(公告)日：2000-05-30

申请号：US162820

申请日：1998-09-29

Applicant: Frank M. Wanlass

Inventor： Frank M. Wanlass

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L29/10 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/76844 ,  H01L21/28088 ,  H01L21/76843 ,  H01L21/76897 ,  H01L29/1045 ,  H01L29/41783 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/4966

Abstract: This invention is a damascene processing method for forming ultra short channel MOS transistors, where the channel length is not determined by photolithograpy. The method uses chemical mechanical polishing to self align an MOS transistor gate electrode to the MOS channel region in both the width and length directions. The method enables metal interconnect lines to make borderless connections to the MOS gate electrodes directly over channel regions, and allows borderless connections to be made to the MOS source and drain regions, thereby improving layout density of small transistors. The method uses metal for first level interconnect lines rather than polysilicon. The method enables the interconnect lines to be patterned on a planar surface, which facilitates the etching of very narrow and closely spaced lines. The method does not require any Shallow Trench Isolation (STI), and does not require Local Oxidation of Silicon (LOCOS), thereby resulting in little damage to the silicon substrate. The method also prevents plasma damage of very thin gate dielectrics during processing.

Abstract translation: 本发明是用于形成超短沟道MOS晶体管的镶嵌处理方法，其中通道长度不由光刻确定。 该方法使用化学机械抛光来将MOS晶体管栅电极在宽度和长度方向上自对准MOS沟道区。 该方法使得金属互连线能够直接通过沟道区域与MOS栅电极无边界连接，并且允许对MOS源极和漏极区进行无边界连接，从而改善小晶体管的布局密度。 该方法使用金属作为一级互连线而不是多晶硅。 该方法使互连线能够在平坦表面上被图案化，这有助于蚀刻非常狭窄和紧密间隔的线。 该方法不需要任何浅沟槽隔离（STI），并且不需要局部氧化硅（LOCOS），从而对硅衬底几乎没有损坏。 该方法还可以防止非常薄的栅极电介质在处理过程中的等离子体损伤。

公开(公告)号：US5319260A

公开(公告)日：1994-06-07

申请号：US964490

申请日：1992-10-20

Applicant: Frank M. Wanlass

Inventor： Frank M. Wanlass

IPC: H03K17/16

CPC classification number: H03K17/167

Abstract: A CMOS device having many output channels at least one of which channel includes a first pair of pull-up/pull-down of transistors between a "noisy Vcc and noisy ground", a second pair of pull-up/pull-down of transistors between a "quiet Vcc and quiet ground", and logic to switch the transistor pairs such that initial switching of an output is powered by the noisy Vcc and ground, and maintenance of an output state is powered by the quiet Vcc and ground. Quiescent channels are decoupled from active channels and will hold their assigned output levels.

Abstract translation: 具有许多输出通道的CMOS器件，其中至少一个通道包括在“噪声Vcc和噪声接地”之间的晶体管的第一对上拉/下拉，晶体管的第二对上拉/下拉 在“安静的Vcc和静音地”之间，以及切换晶体管对的逻辑，使得输出的初始切换由噪声Vcc和地面供电，并且输出状态的维持由静音Vcc和地面供电。 静态通道与有源通道分离，并保持其分配的输出电平。

公开(公告)号：US5311083A

公开(公告)日：1994-05-10

申请号：US008669

申请日：1993-01-25

Applicant: Frank M. Wanlass

Inventor： Frank M. Wanlass

IPC: H03K19/0175 ,  G11C11/401 ,  H03K3/3565 ,  H03K17/0814 ,  H03K17/16 ,  H03K19/003 ,  H03K19/0185 ,  H03K9/0177

CPC classification number: H03K3/3565 ,  H03K17/08142 ,  H03K17/162 ,  H03K19/00315 ,  H03K19/00361 ,  H03K19/018521 ,  H03K19/018592

Abstract: A CMOS integrated circuit (IC) deviceembodiment of the present invention comprises an internal logic circuit operating with traditional 3.3 volt or five volt internal logic levels, an output buffer to convert the internal logic levels to external logic levels of 0.3 volts and an input buffer to convert the 0.3 volt external logic levels to the internal logic levels. In a CMOS IC device having numerous external output loads including relatively high capacitive values that are driven at very high clock rates, the restricted voltage swings of the 0.3 volt external logic levels permit unusually large numbers of devices to be driven without exceeding a predetermined power dissipation limit of the CMOS IC device. The low external logic levels further permit electrostatic discharge (ESD) protection to be included on all signal inputs and outputs of the CMOS IC device. The ESD protection comprises a pair of opposite polarity silicon PN junction diodes in parallel and connected between each signal line and a ground reference.

Abstract translation: 本发明的CMOS集成电路（IC）器件实施例包括一个内部逻辑电路，其工作于传统的3.3伏特或五伏内部逻辑电平，一个输出缓冲器将内部逻辑电平转换为0.3伏的外部逻辑电平，以及一个输入缓冲器 将0.3伏外部逻辑电平转换为内部逻辑电平。 在具有许多外部输出负载的CMOS IC器件中，包括以非常高的时钟速率驱动的相对较高的电容值，0.3伏外部逻辑电平的受限电压摆幅允许异常大量的器件被驱动而不超过预定的功耗 CMOS IC器件的极限。 低的外部逻辑电平进一步允许静电放电（ESD）保护被包括在CMOS IC器件的所有信号输入和输出端。 ESD保护包括并联的一对相反极性的硅PN结二极管，并且连接在每个信号线和接地基准之间。

公开(公告)号：US4425516A

公开(公告)日：1984-01-10

申请号：US259651

申请日：1981-05-01

Applicant: Frank M. Wanlass

Inventor： Frank M. Wanlass

IPC: H01L27/06 ,  H01L27/092 ,  H03K5/151 ,  H03K19/0944 ,  H03K17/04 ,  H03K17/62 ,  H03K17/693 ,  H03K19/092

CPC classification number: H01L27/0623 ,  H01L27/092 ,  H03K19/09448 ,  H03K5/151

Abstract: A monolithic integrated circuit structure consisting of interconnected bipolar and CMOS transistor elements forming a buffer circuit. A pair of NPN bipolar transistor elements are interconnected with a pair of N-type MOS transistor elements to form a push-pull output stage providing complementary outputs at the emitters of the bipolar transistor elements. Each of the pair of NPN bipolar transistor elements is arranged in an emitter follower circuit configuration having the conducting channel of one of the pair of N-type MOS transistor elements serially connected to its emitter. The gate electrode of each of the pair of MOS transistor elements respectively is connected to the emitter of the bipolar transistor element to which the conducting channel of the other of the pair of MOS transistor elements is connected. P-type and N-type MOS transistor elements are serially interconnected in a complementary symmetry manner to form an inverter circuit configuration. The complementary interconnected MOS transistor elements have their drains connected together to the base of one of the pair of bipolar transistor elements and their gate electrodes connected together to the base of the other of the pair of bipolar transistor elements, the connected gate electrodes and base forming the buffer circuit input. The collectors of the bipolar transistor elements and the source of the P-type MOS transistor element are connected together to define a positive supply voltage terminal and the sources of the N-type MOS transistor elements are connected together to define a reference potential terminal.

Abstract translation: 由互连的双极和CMOS晶体管元件组成的单片集成电路结构，形成缓冲电路。 一对NPN双极晶体管元件与一对N型MOS晶体管元件互连，以形成在双极晶体管元件的发射极处提供互补输出的推挽输出级。 一对NPN双极晶体管元件中的每一个被配置为具有串联连接到其发射极的一对N型MOS晶体管元件中的一个的导通沟道的射极跟随器电路结构。 所述一对MOS晶体管元件中的每一个的栅电极分别与所述双极晶体管元件的发射极连接，所述一对MOS晶体管元件的另一个的导通沟道连接到所述发射极。 P型和N型MOS晶体管元件以互补对称方式串联互连以形成逆变器电路配置。 互补的互连MOS晶体管元件将其漏极连接在一对双极晶体管元件中的一个的基极上，并且它们的栅电极连接在一对双极晶体管元件中另一个的基极上，连接的栅极电极和基底形成 缓冲电路输入。 双极晶体管元件的集电极和P型MOS晶体管元件的源极连接在一起以限定正电源电压端子，并且N型MOS晶体管元件的源极连接在一起以限定参考电位端子。