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    Technique for reducing silicide defects by reducing deleterious effects of particle bombardment prior to silicidation
    11.
    发明授权
    Technique for reducing silicide defects by reducing deleterious effects of particle bombardment prior to silicidation 失效
    通过减少硅化物之前的粒子轰击的有害影响来减少硅化物缺陷的技术

    公开(公告)号：US07384877B2

    公开(公告)日：2008-06-10

    申请号：US11419540

    申请日：2006-05-22

    申请人： Volker Kahlert ,  Christof Streck ,  Patrick Press

    发明人： Volker Kahlert ,  Christof Streck ,  Patrick Press

    IPC分类号： H01L21/302

    CPC分类号： H01L21/02057 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665

    摘要： By reducing the effect of particle bombardment during the sequence for forming a metal silicide in semiconductor devices, the defect rate and the metal silicide uniformity may be enhanced. For this purpose, the metal may be deposited without an immediately preceding sputter etch process, wherein, in a particular embodiment, an additional oxidation process is performed to efficiently remove any silicon contaminations and surface impurities by a subsequent wet chemical treatment on the basis of HF, which is followed by the metal deposition.

    摘要翻译： 通过减少在半导体器件中形成金属硅化物的顺序期间的粒子轰击的影响，可以提高缺陷率和金属硅化物的均匀性。 为了这个目的，金属可以在没有紧接在前的溅射蚀刻工艺的情况下沉积，其中在特定实施例中，执行额外的氧化工艺以通过基于HF的随后的湿化学处理来有效地去除任何硅污染物和表面杂质 ，其后是金属沉积。

    SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN
    14.
    发明申请
    SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN 有权
    包含用于创建拉伸和压缩应变的嵌入式SI / GE材料的NMOS和PMOS晶体管的半导体器件

    公开(公告)号：US20080099794A1

    公开(公告)日：2008-05-01

    申请号：US11748902

    申请日：2007-05-15

    申请人： Sven Beyer ,  Manfred Horstmann ,  Patrick Press ,  Wolfgang Buchholtz

    发明人： Sven Beyer ,  Manfred Horstmann ,  Patrick Press ,  Wolfgang Buchholtz

    IPC分类号： H01L29/04 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L29/165 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/7849

    摘要： By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.

    摘要翻译： 通过在一个有源区中形成基本上连续且均匀的半导体合金，同时在第二有源区中图案化半导体合金，以便在其中心部分提供基极半导体材料，可以诱发不同类型的应变， 可以使用基底半导体材料的相应的覆盖层，用于形成栅极电介质的完善的工艺技术。 在一些说明性实施例中，提供了基本上自对准的工艺，其中栅电极可以基于层形成，其也已经用于限定一个有源区的基极半导体材料的中心部分。 因此，通过使用单个半导体合金，可以单独提高不同导电类型的晶体管的性能。

    Method of boron doping wafers using a vertical oven system
    16.
    发明授权
    Method of boron doping wafers using a vertical oven system 失效
    使用立式烤箱系统的硼掺杂晶圆的方法

    公开(公告)号：US06548378B1

    公开(公告)日：2003-04-15

    申请号：US09868324

    申请日：2001-08-30

    申请人： Henning Boness ,  Patrick Press

    发明人： Henning Boness ,  Patrick Press

    IPC分类号： H01L2126

    CPC分类号： H01L21/67109 ,  C23C16/28 ,  C23C16/46 ,  C23C16/56 ,  C30B31/06 ,  C30B31/12

    摘要： The present invention relates to a method for boron doping wafers using a vertical oven system. The vertical oven system (1) used comprises a vertical reaction chamber (2) that extends from an upper end toward a lower end and comprises several independently heated temperature zones (5a-5e). An upper temperature zone (5a) is provided on a gas intake (6) for a boron-containing reactive gas. The additional zones (5b-5e) follow the upper end in the direction toward the lower end of the reaction chamber (2). With this method, the boron-containing reactive gas flows over the wafers (4) inside the reaction chamber. The boron from the boron layer, deposited in this way on the wafers, subsequently diffuses into the wafer surface. The method according to the invention provides that the temperature of the additional zones (5b-5e) is adjusted such that it is possible to maintain a temperature increase during the deposit across the additional zones and a temperature drop toward the lower end of the reaction chamber (2) during the diffusion across the additional zones. A high uniformity of the produced doping profile can thus be achieved across the individual wafers as well as across the reaction chamber. The same is true for the reproducibility of the doping profile between individual process cycles.

    摘要翻译： 本发明涉及一种使用立式烤箱系统进行掺硼的方法。 使用的立式烤箱系统（1）包括从上端向下端延伸的竖直反应室（2），其包括数个独立加热的温度区（5a-5e）。 在用于含硼反应气体的气体入口（6）上设置有上部温度区（5a）。 附加区域（5b-5e）沿着朝向反应室（2）的下端的方向的上端。 通过该方法，含硼的反应性气体流过反应室内的晶片（4）。 以这种方式沉积在晶片上的来自硼层的硼随后扩散到晶片表面。 根据本发明的方法提供了调节附加区域（5b-5e）的温度，使得可以在跨越附加区域的沉积期间保持温度升高，并且朝向反应室的下端的温度下降 （2）在扩散跨越附加区域。 因此，可以在单个晶片以及整个反应室上实现所产生的掺杂分布的高均匀性。 对于各个工艺循环之间的掺杂分布的再现性也是如此。

    SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN
    18.
    发明申请
    SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN 有权
    包含用于创建拉伸和压缩应变的嵌入式SI / GE材料的NMOS和PMOS晶体管的半导体器件

    公开(公告)号：US20110104878A1

    公开(公告)日：2011-05-05

    申请号：US13005676

    申请日：2011-01-13

    申请人： Sven Beyer ,  Manfred Horstmann ,  Patrick Press ,  Wolfgang Buchholtz

    发明人： Sven Beyer ,  Manfred Horstmann ,  Patrick Press ,  Wolfgang Buchholtz

    IPC分类号： H01L21/20

    CPC分类号： H01L21/823807 ,  H01L29/165 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/7849

    摘要： By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.

    摘要翻译： 通过在一个有源区中形成基本上连续且均匀的半导体合金，同时在第二有源区中图案化半导体合金，以便在其中心部分提供基极半导体材料，可以诱发不同类型的应变， 可以使用基底半导体材料的相应的覆盖层，用于形成栅极电介质的完善的工艺技术。 在一些示例性实施例中，提供了基本上自对准的工艺，其中栅电极可以基于层形成，其也已经用于限定一个有源区的基极半导体材料的中心部分。 因此，通过使用单个半导体合金，可以单独提高不同导电类型的晶体管的性能。

    MULTIPLE GATE TRANSISTOR HAVING HOMOGENOUSLY SILICIDED FIN END PORTIONS
    20.
    发明申请
    MULTIPLE GATE TRANSISTOR HAVING HOMOGENOUSLY SILICIDED FIN END PORTIONS 有权
    具有均质硅胶端部的多栅极晶体管

    公开(公告)号：US20100133614A1

    公开(公告)日：2010-06-03

    申请号：US12620083

    申请日：2009-11-17

    申请人： Sven Beyer ,  Patrick Press ,  Rainer Giedigkeit ,  Jan Hoentschel

    发明人： Sven Beyer ,  Patrick Press ,  Rainer Giedigkeit ,  Jan Hoentschel

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/321 ,  H01L29/06

    CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795

    摘要： In a multiple gate transistor, the plurality of Fins of the drain or source of the transistor are electrically connected to each other by means of a common contact element, wherein enhanced uniformity of the corresponding contact regions may be accomplished by an enhanced silicidation process sequence. For this purpose, the Fins may be embedded into a dielectric material in which an appropriate contact opening may be formed to expose end faces of the Fins, which may then act as silicidation surface areas.

    摘要翻译： 在多栅极晶体管中，晶体管的漏极或源极的多个鳍状物通过公共接触元件彼此电连接，其中相应的接触区域的增强的均匀性可以通过增强的硅化工艺序列来实现。 为此，金箔可以嵌入电介质材料中，其中可以形成适当的接触开口以露出金属丝的端面，其然后可以作为硅化表面区域。