公开(公告)号：US09176159B2

公开(公告)日：2015-11-03

申请号：US14045476

申请日：2013-10-03

Applicant: Freescale Semiconductor, Inc.

Inventor： William E. Edwards ,  Mike R. Garrard

IPC: G01B7/30 ,  G01P3/488 ,  G01D1/00 ,  G01D5/20 ,  B60R1/00 ,  F16H27/00

CPC classification number: G01P3/488 ,  B60R1/00 ,  F16H27/00 ,  G01D1/00 ,  G01D5/20 ,  H01L2221/00

Abstract: The embodiments described herein can provide a variable reluctance sensor (VRS) interface that may reduce the probability of erroneous transitions in a resulting generated detect signal. As such, the VRS interface can improve the accuracy of position and/or motion determinations, and thus can improve the performance of a wide variety of devices that use variable reluctance sensors. To facilitate this, the VRS interface includes a pre-processing circuit configured to modify a VRS signal to prevent the modified VRS signal from dropping below a threshold value and generating erroneous transitions in the detect signal pulse between leading and lagging edges of a tooth. In one embodiment the pre-processing circuit comprises a peak and hold circuit. In another embodiment the pre-processing circuit comprises a resistor-capacitor circuit. In either case the pre-processing circuit can prevent erroneous transitions in the detect signal and thus may improve the performance and accuracy of the system.

Abstract translation: 这里描述的实施例可以提供可变磁阻传感器（VRS）接口，其可以降低产生的所产生的检测信号中的错误转换的可能性。 因此，VRS接口可以提高位置和/或运动确定的精度，从而可以提高使用可变磁阻传感器的各种各样的设备的性能。 为了实现这一点，VRS接口包括预处理电路，其被配置为修改VRS信号以防止修改的VRS信号降低到阈值以下并且在牙齿的前沿和滞后边缘之间的检测信号脉冲中产生错误的转变。 在一个实施例中，预处理电路包括峰值和保持电路。 在另一个实施例中，预处理电路包括电阻 - 电容电路。 在任一种情况下，预处理电路可以防止检测信号中的错误转换，从而可以提高系统的性能和精度。

公开(公告)号：US20150198666A1

公开(公告)日：2015-07-16

申请号：US14152262

申请日：2014-01-10

Applicant: Freescale Semiconductor, Inc.

Inventor： William E. Edwards ,  Anthony F. Andresen ,  Randall C. Gray

IPC: G01R31/327

CPC classification number: G01R31/327 ,  H03K17/18

Abstract: A method of switch detection is disclosed that comprises, enabling a low power mode on a switch detection device, activating a first detection circuit for detecting, at a first expiration of a first polling time interval, a first switch state of a first switch having a first priority level, the first switch state including one of a first open state and a first closed state, comparing the detected first switch state with a prior first switch state, and activating a second detection circuit for detecting, at a second expiration of a second polling time interval, a second switch state of a second switch having a second priority level, the second switch including one of a second open state and a second closed state, and the second polling time interval being greater than the first polling time interval, and the second priority level being different from the first priority level.

Abstract translation: 公开了一种开关检测方法，其特征在于包括：在开关检测装置上实现低功率模式，激活第一检测电路，用于在第一轮询时间间隔的第一次到期时检测具有第一开关的第一开关的第一开关状态， 第一优先级，第一开关状态包括第一打开状态和第一关闭状态之一，将检测到的第一开关状态与先前的第一开关状态进行比较，以及激活第二检测电路，用于在第二优先级的第二次到期时检测 轮询时间间隔，具有第二优先级的第二交换机的第二切换状态，所述第二交换机包括第二打开状态和第二关闭状态中的一个，所述第二轮询时间间隔大于所述第一轮询时间间隔，以及 第二优先级与第一优先级不同。

公开(公告)号：US09970405B2

公开(公告)日：2018-05-15

申请号：US15104246

申请日：2013-12-16

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Michael Robert Garrard ,  William E. Edwards ,  John Matthew Hall

IPC: F02P5/15 ,  F02P5/145 ,  F02P9/00 ,  F02P3/06 ,  G01P3/36 ,  G01P3/44 ,  H02P6/16 ,  H02P27/08 ,  F02P5/00 ,  F02D41/24

CPC classification number: F02P5/1514 ,  F02D41/2416 ,  F02D2400/06 ,  F02P3/06 ,  F02P5/145 ,  F02P9/005 ,  G01P3/36 ,  G01P3/44 ,  H02P6/16 ,  H02P27/08 ,  Y02T10/46

Abstract: A control methodology and apparatus for an engine suitable for use in capacitor discharge ignition systems for internal combustion engines or brushless DC motors is provided, which make use of a simple logic block to determine for instance an ignition timing advance angle or duty cycle signal based on actual engine speed versus engine control parameter data stored in a table, which is a read-only memory, preferably configurable. To minimize memory space, a small number of values of engine control parameter versus engine speed are stored in the table and the logic block determines the required engine control signal for a measured value of engine speed by an interpolation process, preferably linear interpolation.

公开(公告)号：US09726519B2

公开(公告)日：2017-08-08

申请号：US14156034

申请日：2014-01-15

Applicant: Freescale Semiconductor, Inc.

Inventor： Mike R. Garrard ,  William E. Edwards

IPC: G01D5/20 ,  F02P7/067 ,  F02P5/145 ,  G01B7/14 ,  F02P1/00

CPC classification number: G01D5/2013 ,  F02P1/00 ,  F02P5/145 ,  F02P7/0675 ,  G01B7/14

Abstract: The embodiments described herein include systems with a variable reluctance sensor (VRS) interface and methods of their operation. Embodiments of VRS interfaces include a clearing signal generator configured to generate a clearing signal corresponding with the timing of a noise event. The clearing signal may be configured to clear a post-processing circuit.

公开(公告)号：US20170091139A1

公开(公告)日：2017-03-30

申请号：US14870770

申请日：2015-09-30

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： William E. Edwards ,  Jesse R. Beeker

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G06F13/16 ,  G06F13/24 ,  G06F13/4027

Abstract: A method and apparatus provide an ability to selectively couple one of the output of the buffer or the output of the digital driver to a data terminal based upon a state of a storage location in which a stored first select indicator is stored and based upon a state of a selection signal. An external serial interface, at a semiconductor die, includes the data terminal, a selection terminal to receive the selection signal, and a clock terminal to receive a clock signal. A buffer includes an input to receive a secondary signal and an output to provide the secondary signal to the data terminal. A digital driver includes a digital output coupled to the data terminal. A first storage location has a storage state based upon the stored first select indicator. Select circuitry provides the selectively coupling.