公开(公告)号：US10817528B2

公开(公告)日：2020-10-27

申请号：US15365755

申请日：2016-11-30

Applicant: Futurewei Technologies, Inc.

Inventor： Ashish Rai Shrivastava ,  Alex Elisa Chandra ,  Mark Brown ,  Debashis Bhattacharya ,  Alan Gatherer

IPC: G06F16/25 ,  G06F16/21 ,  G06F16/28

Abstract: A data warehouse engine (DWE) includes a central processing unit (CPU) core and a first data organization unit (DOU), where the first DOU is configured to aggregate read operations. The DWE also includes a first command queue coupled between the CPU core and the first DOU, where the first command queue is configured to convey commands from the CPU core to the first DOU.

公开(公告)号：US10289598B2

公开(公告)日：2019-05-14

申请号：US15096982

申请日：2016-04-12

Applicant: Futurewei Technologies, Inc.

Inventor： Peter Yan ,  Alex Elisa Chandra ,  YwhPyng Harn ,  Xiaotao Chen ,  Alan Gatherer ,  Fang Yu ,  Xingfeng Chen ,  Zhuolei Wang ,  Yang Zhou

IPC: G06F13/38 ,  G06F13/42 ,  G06F13/40

Abstract: A described embodiment of the present invention includes a network having a first, second and third plurality of routers connected to a plurality of endpoints. At least one of the first plurality of routers includes a plurality of interposers having a number of queues. The at least one of the first plurality of routers has a demultiplexer for each interposer configured to receive multiplexed data from the interposer and provide demultiplexed data on to a plurality of second queues corresponding to the first queues of the number of queues. The at least one of the first plurality of routers also includes a number multiplexers, each of the number multiplexers having inputs configured to receive data from the number of queues.

公开(公告)号：US20180300258A1

公开(公告)日：2018-10-18

申请号：US15486699

申请日：2017-04-13

Applicant: Futurewei Technologies, Inc.

Inventor： Sushma Wokhlu ,  Alex Elisa Chandra ,  Alan Gatherer

IPC: G06F12/126

Abstract: A method of operating a cache memory comprises receiving a first read or write command including at least a first address referring to first data and a first rank indicator associated with the first data, and in response to receiving the first read or write command, reading or writing the first data referenced by the first address, and storing the first rank indicator.

公开(公告)号：US20170293512A1

公开(公告)日：2017-10-12

申请号：US15096966

申请日：2016-04-12

Applicant: Futurewei Technologies, Inc.

Inventor： Peter Yan ,  Alan Gatherer ,  Alex Elisa Chandra ,  Lee Dobson Mcfearin ,  Mark Brown ,  Debashis Bhattacharya ,  Fang Yu ,  Xingfeng Chen ,  Yan Bei ,  Ke Ning ,  Chushun Huang ,  Tong Sun ,  Xiaotao Chen

IPC: G06F9/54 ,  G06F13/28

CPC classification number: G06F9/546 ,  G06F13/28

Abstract: Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.