公开(公告)号：US20170293512A1

公开(公告)日：2017-10-12

申请号：US15096966

申请日：2016-04-12

Applicant: Futurewei Technologies, Inc.

Inventor： Peter Yan ,  Alan Gatherer ,  Alex Elisa Chandra ,  Lee Dobson Mcfearin ,  Mark Brown ,  Debashis Bhattacharya ,  Fang Yu ,  Xingfeng Chen ,  Yan Bei ,  Ke Ning ,  Chushun Huang ,  Tong Sun ,  Xiaotao Chen

IPC: G06F9/54 ,  G06F13/28

CPC classification number: G06F9/546 ,  G06F13/28

Abstract: Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.

公开(公告)号：US10185606B2

公开(公告)日：2019-01-22

申请号：US15096966

申请日：2016-04-12

Applicant: Futurewei Technologies, Inc.

Inventor： Peter Yan ,  Alan Gatherer ,  Alex Elisa Chandra ,  Lee Dobson Mcfearin ,  Mark Brown ,  Debashis Bhattacharya ,  Fang Yu ,  Xingfeng Chen ,  Yan Bei ,  Ke Ning ,  Chushun Huang ,  Tong Sun ,  Xiaotao Chen

IPC: G06F3/00 ,  G06F9/44 ,  G06F9/46 ,  G06F13/00 ,  G06F9/54 ,  G06F13/28

Abstract: Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.

公开(公告)号：US10452287B2

公开(公告)日：2019-10-22

申请号：US15192453

申请日：2016-06-24

Applicant: Futurewei Technologies, Inc.

Inventor： Sushma Wokhlu ,  Lee Dobson Mcfearin ,  Alan Gatherer ,  Hao Luan

IPC: G06F3/06 ,  G06F12/084 ,  G06F12/0888 ,  G06F12/14 ,  G06F9/50 ,  G06F12/0815

Abstract: It is possible to reduce the latency attributable to memory protection in shared memory systems by performing access protection at a central Data Ownership Manager (DOM), rather than at distributed memory management units in the central processing unit (CPU) elements (CEs) responsible for parallel thread processing. In particular, the DOM may monitor read requests communicated over a data plane between the CEs and a memory controller, and perform access protection verification in parallel with the memory controller's generation of the data response. The DOM may be separate and distinct from both the CEs and the memory controller, and therefore may generally be able to make the access determination without interfering with data plane processing/generation of the read requests and data responses exchanged between the memory controller and the CEs.

公开(公告)号：US20170371570A1

公开(公告)日：2017-12-28

申请号：US15192453

申请日：2016-06-24

Applicant: Futurewei Technologies, Inc.

Inventor： Sushma Wokhlu ,  Lee Dobson Mcfearin ,  Alan Gatherer ,  Hao Luan

IPC: G06F3/06 ,  G06F12/084 ,  G06F12/0815

CPC classification number: G06F3/0619 ,  G06F3/0637 ,  G06F3/0673 ,  G06F9/50 ,  G06F9/5016 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0888 ,  G06F12/1466 ,  G06F2212/621

Abstract: It is possible to reduce the latency attributable to memory protection in shared memory systems by performing access protection at a central Data Ownership Manager (DOM), rather than at distributed memory management units in the central processing unit (CPU) elements (CEs) responsible for parallel thread processing. In particular, the DOM may monitor read requests communicated over a data plane between the CEs and a memory controller, and perform access protection verification in parallel with the memory controller's generation of the data response. The DOM may be separate and distinct from both the CEs and the memory controller, and therefore may generally be able to make the access determination without interfering with data plane processing/generation of the read requests and data responses exchanged between the memory controller and the CEs.