公开(公告)号：US20150040091A1

公开(公告)日：2015-02-05

申请号：US13955300

申请日：2013-07-31

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ayman Hamouda

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G03F1/36 ,  G03F7/70441 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/72

Abstract: Methods for modifying a layout design of an integrated circuit are provided. In one embodiment, a method for modifying an integrated circuit layout design includes providing an initial circuit layout design comprising a lower metal layer, an upper metal layer, and a first via electrically connecting the lower metal layer to the upper metal layer. The method further includes altering the initial circuit layout design by providing a second via, the second via being in electrical contact with no more than one of the upper metal layer and the lower metal layer, and the second via further being in proximity to the first via. Further, the method includes further altering the initial circuit layout design by providing a subresolution assist feature in proximity to the second via.

Abstract translation: 提供了修改集成电路布局设计的方法。 在一个实施例中，一种用于修改集成电路布局设计的方法包括提供包括下金属层，上金属层和将下金属层电连接到上金属层的第一通孔的初始电路布局设计。 该方法还包括通过提供第二通孔来改变初始电路布局设计，第二通孔与上金属层和下金属层中的不超过一个电接触，并且第二通孔进一步靠近第一通孔 通过。 此外，该方法还包括通过在第二通孔附近提供副分辨率辅助特征来进一步改变初始电路布局设计。

公开(公告)号：US10831977B1

公开(公告)日：2020-11-10

申请号：US16429536

申请日：2019-06-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mohamed Elsayed Mohamed Lotfy Gheith ,  Ian Stobert ,  Ayman Hamouda

IPC: G06F30/398 ,  G03F1/70 ,  G06N20/00 ,  G06F119/18

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to curvilinear mask models and methods of manufacture. The method includes: calibrating, by a computing device, machine learning models for silicon photonics applications; retargeting, by the computing device, designs in a layout for the silicon photonics applications by applying the machine learning models to the designs; and repairing, by the computing device, unmatching shapes in the retargeted designs to generate final curvilinear mask shapes for the silicon photonics application.

公开(公告)号：US10345694B2

公开(公告)日：2019-07-09

申请号：US15658721

申请日：2017-07-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ayman Hamouda

IPC: G03F1/36 ,  G06F17/50 ,  G03F1/00

Abstract: Approaches herein provide model-based generation of dummy features used during processing of a semiconductor device (e.g., during a self-aligned via process). Specifically, at least one approach includes: generating a set of dummy features in proximity to a set of target features in a mask layout, evaluating a proximity of the set of dummy features to a metal layer of the semiconductor device, and removing a portion of the set of dummy features that is present within an established critical distance between the set of dummy features and the metal layer. Target design printability is further enhanced during photolithography by performing one or more of the following: merging two or more dummy features of the set of dummy features, and increasing a distance between adjacent dummy features of the set of dummy features by modifying a geometry of one or more of the set of dummy features.

公开(公告)号：US09747401B2

公开(公告)日：2017-08-29

申请号：US15078032

申请日：2016-03-23

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ayman Hamouda

IPC: G06F17/50 ,  G03F1/36 ,  G03F7/20

CPC classification number: G06F17/5068 ,  G03F1/36 ,  G03F7/70441 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/72

Abstract: A method for modifying an integrated circuit layout design includes providing an initial multiple-patterned circuit layout design comprising a first pattern exposure and a second pattern exposure; modifying the initial multiple-patterned circuit layout design by providing a subresolution assist feature to the first pattern exposure; determining whether the presence of any overlapping areas between the subresolution assist feature of the first pattern exposure and the second pattern exposure; and further modifying the initial multiple-patterned circuit layout design by: maintaining the size of any portion of the subresolution assist feature in the overlapping areas; and shrinking the size of any portion of the subresolution assist feature that is not in the overlapping areas.

公开(公告)号：US09443055B2

公开(公告)日：2016-09-13

申请号：US14699705

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ayman Hamouda ,  Chidam Kallingal ,  Norman Chen

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/70 ,  G06F2217/12 ,  Y02P90/265

Abstract: Methods for retargeting a circuit design layout for a multiple patterning lithography process and for fabricating a semiconductor device are provided. In an exemplary embodiment, a computer-executed method for retargeting a circuit design layout for a multiple patterning lithography process is provided. The method includes decomposing a circuit design layout file to produce decomposed layout files in a computer. Each decomposed layout file is associated with a respective mask for use in the multiple patterning lithography process. The method includes preparing retargeted layout files in the computer by retargeting selected decomposed layout files based on photolithography limitations specific to each selected decomposed layout file to produce retargeted layout files. Also, the method includes determining in the computer that a combination of layout files includes a spacing conflict. The method further includes resolving the spacing conflict in the computer by modifying the layout file or layout files causing the spacing conflict.

Abstract translation: 提供了用于重新定位用于多图案化光刻工艺的电路设计布局和用于制造半导体器件的方法。 在示例性实施例中，提供了一种用于重新定位用于多图案化光刻工艺的电路设计布局的计算机执行方法。 该方法包括分解电路设计布局文件以在计算机中产生分解的布局文件。 每个分解的布局文件与用于多图案化光刻工艺中的相应掩模相关联。 该方法包括通过基于每个选择的分解布局文件特有的光刻限制重新定位所选择的分解布局文件以产生重定向布局文件来在计算机中准备重定向布局文件。 此外，该方法包括在计算机中确定布局文件的组合包括间隔冲突。 该方法还包括通过修改导致间隔冲突的布局文件或布局文件来解决计算机中的间隔冲突。

公开(公告)号：US20160162621A1

公开(公告)日：2016-06-09

申请号：US14563475

申请日：2014-12-08

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ayman Hamouda

IPC: G06F17/50 ,  H01L21/768

CPC classification number: G06F17/5077 ,  G03F7/70433 ,  G03F7/70625 ,  G03F7/70633 ,  G06F17/5081 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for retargeting a via and for fabricating a semiconductor device with a retargeted via are provided. In one embodiment, a method for retargeting a via includes drawing a lower metal layer shape, drawing a via shape for overlying the lower metal layer shape, and drawing an upper metal layer shape for overlying the via shape to create an interconnection area between the via shape and the upper metal layer shape. The method includes determining a potential area loss of the interconnection area during integrated circuit fabrication processing. The method further includes enlarging the via shape to compensate for the potential area loss.

Abstract translation: 提供了用于重定向通孔和用于制造具有重定向通孔的半导体器件的方法。 在一个实施例中，用于重新定位通孔的方法包括：绘制下部金属层形状，绘制用于覆盖下部金属层形状的通孔形状，以及画出用于覆盖通孔形状的上部金属层形状，以在通孔 形状和上层金属层形状。 该方法包括在集成电路制造处理期间确定互连区域的潜在面积损耗。 该方法还包括扩大通孔形状以补偿潜在的面积损耗。

公开(公告)号：US09317645B2

公开(公告)日：2016-04-19

申请号：US13955300

申请日：2013-07-31

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ayman Hamouda

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G03F1/36 ,  G03F7/70441 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/72

Abstract: Methods for modifying a layout design of an integrated circuit are provided. In one embodiment, a method for modifying an integrated circuit layout design includes providing an initial circuit layout design comprising a lower metal layer, an upper metal layer, and a first via electrically connecting the lower metal layer to the upper metal layer. The method further includes altering the initial circuit layout design by providing a second via, the second via being in electrical contact with no more than one of the upper metal layer and the lower metal layer, and the second via further being in proximity to the first via. Further, the method includes further altering the initial circuit layout design by providing a subresolution assist feature in proximity to the second via.

Abstract translation: 提供了修改集成电路布局设计的方法。 在一个实施例中，一种用于修改集成电路布局设计的方法包括提供包括下金属层，上金属层和将下金属层电连接到上金属层的第一通孔的初始电路布局设计。 该方法还包括通过提供第二通孔来改变初始电路布局设计，第二通孔与上金属层和下金属层中的不超过一个电接触，并且第二通孔进一步靠近第一通孔 通过。 此外，该方法还包括通过在第二通孔附近提供副分辨率辅助特征来进一步改变初始电路布局设计。

公开(公告)号：US20160063167A1

公开(公告)日：2016-03-03

申请号：US14469886

申请日：2014-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ayman Hamouda

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5081 ,  H01L23/5226

Abstract: Embodiments of the present invention provide a system and method for SAV (self-aligned via) retargeting. The SAV (Self Aligned Vias) process aids in the alignment of the vias with the metal above (Mx+1) during the dual damascene process. The retargeting enables an increase the area of the via during photolithography without affecting the final critical dimension. SAV retargeting is the via retargeting during the mask tape-out to reshape the via and protect it against possible via-to-Mx+1 overlay error. With embodiments of the present invention, the via edge movement is linked to the actual driver behind the SAV retargeting, which is maintaining a minimum area coverage with the metal above at extreme overlay error conditions. Accordingly, for a via edge to get SAV retargeted, a calculation is first made to determine how much its opposite via edge is subject to be cut during SAV due to overlay error.

Abstract translation: 本发明的实施例提供了一种用于SAV（自对准通孔）重定向的系统和方法。 SAV（自对准通风孔）工艺有助于在双镶嵌工艺期间通孔与金属（Mx + 1）的对准。 重新定向能够在光刻期间增加通孔的面积，而不影响最终临界尺寸。 SAV重新定位是在屏蔽磁带输出期间的通过重定向，以重新整形通道，并保护它免受可能的通过Mx + 1覆盖错误。 利用本发明的实施例，通过边缘移动连接到SAV重新定向后的实际驱动器，SAV重新定向在极端重叠错误条件下保持与上述金属的最小面​​积覆盖。 因此，为了获得SAV重新定向的通孔边缘，首先进行计算，以确定由于覆盖误差而在SAV期间通过边缘相对的边缘被切割多少。

公开(公告)号：US20150040080A1

公开(公告)日：2015-02-05

申请号：US13955342

申请日：2013-07-31

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ayman Hamouda ,  Mohab Anis

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068

Abstract: Methods for modifying a layout design of an integrated circuit using model-based retargeting are provided. In one embodiment, a method for modifying an integrated circuit layout design includes providing an initial integrated circuit layout design, correcting the initial layout design for etch-induced lithography errors to generate an etch-corrected layout design, and fragmenting the etch-corrected layout design to generate a fragmented layout design comprising a plurality of fragments. The method further includes performing a bridging condition simulation and a pinching condition simulation on the fragmented layout design and calculating a required movement for at least one fragment of the fragmented layout design based on the bridging condition simulation and the pinching condition simulation. Still further, the method includes modifying the fragmented layout design by moving the at least one fragment in accordance with the required movement to generate a modified layout design and performing optical proximity correction on the modified layout design.

Abstract translation: 提供了使用基于模型的重定向来修改集成电路的布局设计的方法。 在一个实施例中，用于修改集成电路布局设计的方法包括提供初始集成电路布局设计，校正蚀刻诱导的光刻误差的初始布局设计以产生经蚀刻校正的布局设计，以及将经蚀刻校正的布局设计 以产生包括多个片段的分段布局设计。 该方法还包括在分段布局设计上执行桥接条件模拟和压缩条件模拟，并且基于桥接条件模拟和压缩条件模拟来计算分段布局设计的至少一个片段的所需移动。 此外，该方法包括通过根据所需的移动来移动至少一个片段来修改分段布局设计，以生成修改的布局设计并对修改的布局设计执行光学邻近校正。