公开(公告)号：US20160314234A1

公开(公告)日：2016-10-27

申请号：US15078032

申请日：2016-03-23

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ayman Hamouda

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G03F1/36 ,  G03F7/70441 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/72

Abstract: A method for modifying an integrated circuit layout design includes providing an initial multiple-patterned circuit layout design comprising a first pattern exposure and a second pattern exposure; modifying the initial multiple-patterned circuit layout design by providing a subresolution assist feature to the first pattern exposure; determining whether the presence of any overlapping areas between the subresolution assist feature of the first pattern exposure and the second pattern exposure; and further modifying the initial multiple-patterned circuit layout design by: maintaining the size of any portion of the subresolution assist feature in the overlapping areas; and shrinking the size of any portion of the subresolution assist feature that is not in the overlapping areas.

Abstract translation: 一种用于修改集成电路布局设计的方法包括提供包括第一图案曝光和第二图案曝光的初始多图案化电路布局设计; 通过向第一图案曝光提供副分辨率辅助特征来修改初始多图案化电路布局设计; 确定第一图案曝光的副分辨率辅助特征和第二图案曝光之间是否存在任何重叠区域; 并且通过以下方式进一步修改初始多图案化电路布局设计：维持重叠区域中的副分解辅助特征的任何部分的大小; 并且缩小不在重叠区域中的分解辅助特征的任何部分的尺寸。

公开(公告)号：US09672311B2

公开(公告)日：2017-06-06

申请号：US14469886

申请日：2014-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ayman Hamouda

IPC: G06F17/50 ,  H01L23/522

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5081 ,  H01L23/5226

Abstract: Embodiments of the present invention provide a system and method for SAV (self-aligned via) retargeting. The SAV (Self Aligned Vias) process aids in the alignment of the vias with the metal above (Mx+1) during the dual damascene process. The retargeting enables an increase the area of the via during photolithography without affecting the final critical dimension. SAV retargeting is the via retargeting during the mask tape-out to reshape the via and protect it against possible via-to-Mx+1 overlay error. With embodiments of the present invention, the via edge movement is linked to the actual driver behind the SAV retargeting, which is maintaining a minimum area coverage with the metal above at extreme overlay error conditions. Accordingly, for a via edge to get SAV retargeted, a calculation is first made to determine how much its opposite via edge is subject to be cut during SAV due to overlay error.

公开(公告)号：US10262099B2

公开(公告)日：2019-04-16

申请号：US15444899

申请日：2017-02-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ayman Hamouda

IPC: G06F17/50 ,  G03F1/36

Abstract: A method of providing self-aligned via (SAV) awareness in optical proximity correction (OPC) includes identifying non-SAV edges, identifying any lower metal structure that is within a critical distance from the non-SAV edges, and defining replacement non-SAV edges proximate to the lower metal structure using a distance constraint that is evaluated as part of the OPC objective function to redefine the mask solution and relocate at least one non-SAV edge away from the lower metal structure.

公开(公告)号：US09740092B2

公开(公告)日：2017-08-22

申请号：US14467489

申请日：2014-08-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ayman Hamouda

IPC: G06F17/50 ,  G03F1/36 ,  G03F1/00

CPC classification number: G03F1/36 ,  G03F1/144 ,  G06F17/5081

Abstract: Approaches herein provide model-based generation of dummy features used during processing of a semiconductor device (e.g., during a self-aligned via process). Specifically, at least one approach includes: generating a set of dummy features in proximity to a set of target features in a mask layout, evaluating a proximity of the set of dummy features to a metal layer of the semiconductor device, and removing a portion of the set of dummy features that is present within an established critical distance between the set of dummy features and the metal layer. Target design printability is further enhanced during photolithography by performing one or more of the following: merging two or more dummy features of the set of dummy features, and increasing a distance between adjacent dummy features of the set of dummy features by modifying a geometry of one or more of the set of dummy features.

公开(公告)号：US20160055281A1

公开(公告)日：2016-02-25

申请号：US14467489

申请日：2014-08-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ayman Hamouda

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F1/144 ,  G06F17/5081

Abstract: Approaches herein provide model-based generation of dummy features used during processing of a semiconductor device (e.g., during a self-aligned via process). Specifically, at least one approach includes: generating a set of dummy features in proximity to a set of target features in a mask layout, evaluating a proximity of the set of dummy features to a metal layer of the semiconductor device, and removing a portion of the set of dummy features that is present within an established critical distance between the set of dummy features and the metal layer. Target design printability is further enhanced during photolithography by performing one or more of the following: merging two or more dummy features of the set of dummy features, and increasing a distance between adjacent dummy features of the set of dummy features by modifying a geometry of one or more of the set of dummy features.

Abstract translation: 本文中的方法提供了在半导体器件的处理期间（例如，在自对准通孔过程中）期间使用的基于模型的虚拟特征的生成。 具体地，至少一种方法包括：在掩模布局中产生一组邻近一组目标特征的虚拟特征，评估该虚拟特征集合与半导体器件的金属层的接近度，以及去除部分 存在于虚拟特征集合和金属层之间的建立的临界距离内的虚拟特征集合。 在光刻期间，通过执行以下的一个或多个来进一步增强目标设计的可印刷性：合并该虚拟特征集合中的两个或多个虚拟特征，以及通过修改一个虚拟特征的几何来增加虚拟特征集合的相邻虚拟特征之间的距离 或更多的虚拟特征集合。

公开(公告)号：US08881069B1

公开(公告)日：2014-11-04

申请号：US13964022

申请日：2013-08-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ayman Hamouda

IPC: G06F17/50

CPC classification number: G03F1/36 ,  Y02T10/82

Abstract: A method of SRAF printing using etch-aware SRAF print avoidance engines and the resulting device are provided. Embodiments include performing mask to resist simulations for a mask having both a plurality of features to be formed on a substrate and a plurality of sub resolution assist features (SRAFs); detecting SRAFs of the plurality that will print through to a resist; checking dimensions of the detected SRAFs to determine whether one or more of the SRAFs will etch through to the substrate; modifying the one or more of the SRAFs; and forming the mask after the one or more of the SRAFs have been modified.

Abstract translation: 提供了使用蚀刻感知SRAF打印避免引擎和所得到的设备的SRAF打印的方法。 实施例包括执行掩模以抵抗具有要形成在基板上的多个特征的多个子分辨率辅助特征（SRAF）的掩模的模拟; 检测将打印到抗蚀剂的多个的SRAF; 检查检测到的SRAF的尺寸以确定一个或多个SRAF是否将蚀刻到衬底; 修改一个或多个SRAF; 以及在所述一个或多个所述SRAF之后形成所述掩模。

公开(公告)号：US20170322486A1

公开(公告)日：2017-11-09

申请号：US15658721

申请日：2017-07-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ayman Hamouda

IPC: G03F1/36 ,  G06F17/50 ,  G03F1/00

CPC classification number: G03F1/36 ,  G03F1/144 ,  G06F17/5068 ,  G06F17/5081

Abstract: Approaches herein provide model-based generation of dummy features used during processing of a semiconductor device (e.g., during a self-aligned via process). Specifically, at least one approach includes: generating a set of dummy features in proximity to a set of target features in a mask layout, evaluating a proximity of the set of dummy features to a metal layer of the semiconductor device, and removing a portion of the set of dummy features that is present within an established critical distance between the set of dummy features and the metal layer. Target design printability is further enhanced during photolithography by performing one or more of the following: merging two or more dummy features of the set of dummy features, and increasing a distance between adjacent dummy features of the set of dummy features by modifying a geometry of one or more of the set of dummy features.

公开(公告)号：US20160188781A1

公开(公告)日：2016-06-30

申请号：US14699705

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ayman Hamouda ,  Chidam Kallingal ,  Norman Chen

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/70 ,  G06F2217/12 ,  Y02P90/265

Abstract: Methods for retargeting a circuit design layout for a multiple patterning lithography process and for fabricating a semiconductor device are provided. In an exemplary embodiment, a computer-executed method for retargeting a circuit design layout for a multiple patterning lithography process is provided. The method includes decomposing a circuit design layout file to produce decomposed layout files in a computer. Each decomposed layout file is associated with a respective mask for use in the multiple patterning lithography process. The method includes preparing retargeted layout files in the computer by retargeting selected decomposed layout files based on photolithography limitations specific to each selected decomposed layout file to produce retargeted layout files. Also, the method includes determining in the computer that a combination of layout files includes a spacing conflict. The method further includes resolving the spacing conflict in the computer by modifying the layout file or layout files causing the spacing conflict.

Abstract translation: 提供了用于重新定位用于多图案化光刻工艺的电路设计布局和用于制造半导体器件的方法。 在示例性实施例中，提供了一种用于重新定位用于多图案化光刻工艺的电路设计布局的计算机执行方法。 该方法包括分解电路设计布局文件以在计算机中产生分解的布局文件。 每个分解的布局文件与用于多图案化光刻工艺中的相应掩模相关联。 该方法包括通过基于每个选择的分解布局文件特有的光刻限制重新定位所选择的分解布局文件以产生重定向布局文件来在计算机中准备重定向布局文件。 此外，该方法包括在计算机中确定布局文件的组合包括间隔冲突。 该方法还包括通过修改导致间隔冲突的布局文件或布局文件来解决计算机中的间隔冲突。

公开(公告)号：US09378323B1

公开(公告)日：2016-06-28

申请号：US14563475

申请日：2014-12-08

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ayman Hamouda

IPC: G06F17/50 ,  G03F7/20 ,  H01L21/768 ,  H01L23/544

CPC classification number: G06F17/5077 ,  G03F7/70433 ,  G03F7/70625 ,  G03F7/70633 ,  G06F17/5081 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for retargeting a via and for fabricating a semiconductor device with a retargeted via are provided. In one embodiment, a method for retargeting a via includes drawing a lower metal layer shape, drawing a via shape for overlying the lower metal layer shape, and drawing an upper metal layer shape for overlying the via shape to create an interconnection area between the via shape and the upper metal layer shape. The method includes determining a potential area loss of the interconnection area during integrated circuit fabrication processing. The method further includes enlarging the via shape to compensate for the potential area loss.

Abstract translation: 提供了用于重定向通孔和用于制造具有重定向通孔的半导体器件的方法。 在一个实施例中，用于重新定位通孔的方法包括：绘制下部金属层形状，绘制用于覆盖下部金属层形状的通孔形状，以及画出用于覆盖通孔形状的上部金属层形状，以在通孔 形状和上层金属层形状。 该方法包括在集成电路制造处理期间确定互连区域的潜在面积损耗。 该方法还包括扩大通孔形状以补偿潜在的面积损耗。

公开(公告)号：US08997027B2

公开(公告)日：2015-03-31

申请号：US13955342

申请日：2013-07-31

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ayman Hamouda ,  Mohab Anis

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068

Abstract: Methods for modifying a layout design of an integrated circuit using model-based retargeting are provided. In one embodiment, a method for modifying an integrated circuit layout design includes providing an initial integrated circuit layout design, correcting the initial layout design for etch-induced lithography errors to generate an etch-corrected layout design, and fragmenting the etch-corrected layout design to generate a fragmented layout design comprising a plurality of fragments. The method further includes performing a bridging condition simulation and a pinching condition simulation on the fragmented layout design and calculating a required movement for at least one fragment of the fragmented layout design based on the bridging condition simulation and the pinching condition simulation. Still further, the method includes modifying the fragmented layout design by moving the at least one fragment in accordance with the required movement to generate a modified layout design and performing optical proximity correction on the modified layout design.

Abstract translation: 提供了使用基于模型的重定向来修改集成电路的布局设计的方法。 在一个实施例中，用于修改集成电路布局设计的方法包括提供初始集成电路布局设计，校正蚀刻诱导的光刻误差的初始布局设计以产生经蚀刻校正的布局设计，以及将经蚀刻校正的布局设计 以产生包括多个片段的分段布局设计。 该方法还包括在分段布局设计上执行桥接条件模拟和压缩条件模拟，并且基于桥接条件模拟和压缩条件模拟来计算分段布局设计的至少一个片段的所需移动。 此外，该方法包括通过根据所需的移动来移动至少一个片段来修改分段布局设计，以生成修改的布局设计并对修改的布局设计执行光学邻近校正。