公开(公告)号：US20150115371A1

公开(公告)日：2015-04-30

申请号：US14519215

申请日：2014-10-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael GANZ ,  Bingwu LIU ,  Johannes Marinus VAN MEER ,  Sruthi MURALIDHARAN

IPC: H01L29/78 ,  H01L21/3105 ,  H01L21/266 ,  H01L21/324 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/324 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/265 ,  H01L21/266 ,  H01L21/268 ,  H01L21/31055 ,  H01L21/32139 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7851 ,  H01L29/7854

Abstract: The invention provides a method of forming a semiconductor structure, which include: providing an intermediate semiconductor structure having semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate stack disposed over a portion of the fin; forming a silicon nitride layer over portions of the fin that are not located under the gate stack; and after forming the silicon nitride layer, performing one or more ion implantation steps on the intermediate semiconductor structure. The invention also provides a method of forming a semiconductor structure including: providing an intermediate semiconductor structure having a semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate material disposed over the fin; forming, over the fin and gate material of the intermediate semiconductor structure, a gate stack hardmask including an oxide layer; forming a silicon nitride barrier layer on the oxide layer of the gate stack hardmask; performing one or more gate stack hardmask patterning steps; removing the EG oxide layer from portions of the fin that are not located under the gate; and subsequent to removing the EG oxide layer from portions of the fin that are not located under the gate, performing one or more ion implantation steps.

Abstract translation: 本发明提供一种形成半导体结构的方法，其包括：提供具有半导体衬底的中间半导体结构，具有与所述鳍的至少一部分接触的EG氧化物层的鳍和设置在所述鳍的一部分上的栅叠层 翅膀 在所述鳍片的不位于所述栅叠层下方的部分上形成氮化硅层; 并且在形成氮化硅层之后，在中间半导体结构上执行一个或多个离子注入步骤。 本发明还提供一种形成半导体结构的方法，包括：提供具有半导体衬底的中间半导体结构，具有与所述鳍的至少一部分接触的EG氧化物层的鳍和设置在所述鳍上的栅极材料; 在中间半导体结构的鳍和栅极材料之上形成包括氧化物层的栅堆叠硬掩模; 在栅堆叠硬掩模的氧化物层上形成氮化硅阻挡层; 执行一个或多个栅极堆叠硬掩模图案化步骤; 从不在闸门下方的翅片的部分去除EG氧化物层; 并且在从位于栅极下方的鳍片的部分去除EG氧化物层之后，执行一个或多个离子注入步骤。

公开(公告)号：US20180097089A1

公开(公告)日：2018-04-05

申请号：US15821091

申请日：2017-11-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Bingwu LIU

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: Devices and methods of growing unmerged epitaxy for fin field-effect transistor (FinFet) devices are provided. One method includes, for instance: obtaining a wafer having at least one source, at least one drain, and at least one fin; etching to expose at least a portion of the at least one fin; forming at least one sacrificial gate structure; and forming a first layer of an epitaxial growth on the at least one fin. One device includes, for instance: a wafer having at least one source, at least one drain, and at least one fin; a first layer of an epitaxial growth on the at least one fin; at least one second layer of an epitaxial growth superimposing the first layer of an epitaxial growth; and a first contact region over the at least one source and a second contact region over the at least one drain.

公开(公告)号：US20170263733A1

公开(公告)日：2017-09-14

申请号：US15608283

申请日：2017-05-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael GANZ ,  Bingwu LIU ,  Johannes Marinus VAN MEER ,  Sruthi MURALIDHARAN

IPC: H01L29/66 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/02 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/268 ,  H01L21/3105

CPC classification number: H01L21/324 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/265 ,  H01L21/266 ,  H01L21/268 ,  H01L21/31055 ,  H01L21/32139 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7851 ,  H01L29/7854

Abstract: The invention provides a method of forming a semiconductor structure, which include: providing an intermediate semiconductor structure having semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate stack disposed over a portion of the fin; forming a silicon nitride layer over portions of the fin that are not located under the gate stack; and after forming the silicon nitride layer, performing one or more ion implantation steps on the intermediate semiconductor structure. The invention also provides a method of forming a semiconductor structure including: providing an intermediate semiconductor structure having a semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate material disposed over the fin; forming, over the fin and gate material of the intermediate semiconductor structure, a gate stack hardmask including an oxide layer; forming a silicon nitride barrier layer on the oxide layer of the gate stack hardmask; performing one or more gate stack hardmask patterning steps; removing the EG oxide layer from portions of the fin that are not located under the gate; and subsequent to removing the EG oxide layer from portions of the fin that are not located under the gate, performing one or more ion implantation steps.

公开(公告)号：US20170104011A1

公开(公告)日：2017-04-13

申请号：US14878332

申请日：2015-10-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Bingwu LIU

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L27/1207 ,  H01L21/8234 ,  H01L21/84

Abstract: Bulk semiconductor devices are co-fabricated on a bulk semiconductor substrate with SOI devices. The SOI initially covers the entire substrate and is then removed from the bulk device region. The bulk device region has a thicker dielectric on the substrate than the SOI region. The regions are separated by isolation material, and may or may not be co-planar.

公开(公告)号：US20160254180A1

公开(公告)日：2016-09-01

申请号：US14633341

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bingwu LIU ,  Hui ZANG

IPC: H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/308

CPC classification number: H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649

Abstract: A method as set forth herein can include patterning using a first mask an isolation trench at a sidewall to sidewall isolation (SSI) region of a semiconductor structure having a substrate including fins and a main body section, filling the isolation trench at a SSI region with dielectric material, using a second mask to pattern an isolation trench at a single diffusion break (SDB) region, filling the isolation trench at the SDB region with dielectric material, and recessing dielectric material.

Abstract translation: 本文所述的方法可以包括使用第一掩模对具有包括鳍片和主体部分的衬底的半导体结构的侧壁至侧壁隔离（SSI）区域处的隔离沟槽进行图案化，在SSI区域处填充隔离沟槽， 电介质材料，使用第二掩模在单个扩散断裂（SDB）区域上图案化隔离沟槽，用介电材料填充SDB区域处的隔离沟槽，以及凹陷介电材料。

公开(公告)号：US20150380404A1

公开(公告)日：2015-12-31

申请号：US14315602

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Bingwu LIU

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/6656 ,  H01L29/6681

Abstract: A starting non-planar semiconductor structure is provided having a semiconductor substrate, raised semiconductor structures coupled to the substrate, and a layer of isolation material(s) surrounding the raised structures. The isolation layer is recessed to expose about 40 nm to about 70 nm of the raised structures. The increased height of the exposed raised structures, compared to conventional, allows for a taller gate and taller spacers, which reduces undercut under the spacers and short-channel effects from the loss of isolation material in fabrication.

Abstract translation: 提供起始非平面半导体结构，其具有半导体衬底，耦合到衬底的凸起的半导体结构以及围绕凸起结构的隔离材料层。 将隔离层凹入以露出约40nm至约70nm的凸起结构。 与常规的相比，暴露的凸起结构的增加的高度允许更高的栅极和较高的间隔物，这减少了在间隔物下的底切以及由制造中的隔离材料损失引起的短沟道效应。

公开(公告)号：US20150140756A1

公开(公告)日：2015-05-21

申请号：US14084756

申请日：2013-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hong YU ,  Seong Yeol MUN ,  Bingwu LIU ,  Lun ZHAO ,  Richard J. CARTER ,  Manfred ELLER

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: Circuit fabrication methods are provided which include, for example: providing one or more gate structures disposed over a substrate structure, the substrate structure including a first region and a second region; forming a plurality of U-shaped cavities extending into the substrate structure in the first region and the second region thereof, where at least one first cavity of the plurality of U-shaped cavities is disposed adjacent in one gate structure in the first region; and expanding the at least one first cavity further into the substrate structure to at least partially undercut the one gate structure, without expanding at least one second cavity of the plurality of U-shaped cavities, where forming the plurality of U-shaped cavities facilitates fabricating the circuit structure. In one embodiment, the circuit structure includes first and second transistors, having different device architectures, the first transistor having a higher mobility characteristic than the second transistor.

Abstract translation: 提供了电路制造方法，其包括例如：提供设置在衬底结构上方的一个或多个栅极结构，所述衬底结构包括第一区域和第二区域; 在所述第一区域和所述第二区域中形成延伸到所述衬底结构中的多个U形空腔，其中所述多个U形空腔中的至少一个第一空腔邻近所述第一区域中的一个栅极结构设置; 以及将所述至少一个第一空腔进一步扩展到所述衬底结构中以至少部分地切割所述一个栅极结构，而不扩展所述多个U形空腔中的至少一个第二空腔，其中形成所述多个U形空腔有助于制造 电路结构。 在一个实施例中，电路结构包括具有不同器件结构的第一和第二晶体管，第一晶体管具有比第二晶体管更高的迁移率特性。