中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

22 records (took 0.016 seconds)

    Application specific integrated circuit (ASIC) test screens and selection of such screens
    11.
    发明申请
    Application specific integrated circuit (ASIC) test screens and selection of such screens 有权

    公开(公告)号：US20170220727A1

    公开(公告)日：2017-08-03

    申请号：US15012331

    申请日：2016-02-01

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Eric D. Hunt-Schroeder ,  John R. Goss ,  Igor Arsovski ,  Paul J. Grzymkowski

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F2217/64

    Abstract: Various embodiments include approaches for analyzing a customer design for an application specific integrated circuit (ASIC). In some cases, an approach includes: determining performance requirements of the customer design; querying a test screen database for the performance requirements of the customer design, the test screen database having failure thresholds and associated test screens for detecting the failure thresholds for a set of ASIC devices; generating a filter database including select failure thresholds and associated test screens for the performance requirements of the customer design; and selecting a set of test screens from the filter database based upon a yield cost criteria in forming the ASIC.

    Operational amplifier with current-controlled up or down hysteresis
    12.
    发明授权
    Operational amplifier with current-controlled up or down hysteresis 有权

    公开(公告)号：US09654086B1

    公开(公告)日：2017-05-16

    申请号：US14992426

    申请日：2016-01-11

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： John A. Fifield ,  Eric D. Hunt-Schroeder

    IPC: H03K3/02 ,  H03K3/0233 ,  H03K5/24

    CPC classification number: H03K3/02337 ,  H03K3/011 ,  H03K5/2481

    Abstract: Disclosed is an op-amp circuit with current-controlled hysteresis that is insensitive to PVT variations. In the circuit, a digital output signal is output from an output buffer based on the output voltage at an output node of an op-amp. A current source is connected to the input side of the op-amp or one of multiple current sources is selectively connected to the input side and enabled when the digital output signal has a high value to provide falling edge hysteresis. Alternatively, a current source is connected to the reference side of the op-amp or one of multiple current sources is selectively connected to the reference side and enabled when the digital output signal is low to provide rising edge hysteresis. Alternatively, current sources are connected to both the input and reference sides and selectively controlled to provide either falling or rising edge hysteresis.

    Sequential read mode static random access memory (SRAM)
    13.
    发明授权
    Sequential read mode static random access memory (SRAM) 有权

    公开(公告)号：US10796750B2

    公开(公告)日：2020-10-06

    申请号：US16031439

    申请日：2018-07-10

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Igor Arsovski ,  Akhilesh Patil ,  Eric D. Hunt-Schroeder

    IPC: G11C7/12 ,  G11C11/419 ,  G11C11/4074 ,  G11C11/4076

    Abstract: The present disclosure relates to a structure including a sequential mode read controller which is configured to receive a sequential read enable burst signal and a starting word line address, identify consecutive read operations from an array of storage cells accessed via a plurality of word lines, precharge a plurality of bit lines of the storage cells no more than once during the consecutive read operations, and hold a word line of the word lines active throughout the consecutive read operations. The sequential read enable burst signal and a starting word line address are decoded to select a row address and activate the corresponding word line from a plurality of word lines in the array.

    SEQUENTIAL READ MODE STATIC RANDOM ACCESS MEMORY (SRAM)
    14.
    发明申请
    SEQUENTIAL READ MODE STATIC RANDOM ACCESS MEMORY (SRAM) 审中-公开

    公开(公告)号：US20200020388A1

    公开(公告)日：2020-01-16

    申请号：US16031439

    申请日：2018-07-10

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Igor Arsovski ,  Akhilesh Patil ,  Eric D. Hunt-Schroeder

    IPC: G11C11/419 ,  G11C7/12 ,  G11C11/4076 ,  G11C11/4074

    Abstract: The present disclosure relates to a structure including a sequential mode read controller which is configured to receive a sequential read enable burst signal and a starting word line address, identify consecutive read operations from an array of storage cells accessed via a plurality of word lines, precharge a plurality of bit lines of the storage cells no more than once during the consecutive read operations, and hold a word line of the word lines active throughout the consecutive read operations. The sequential read enable burst signal and a starting word line address are decoded to select a row address and activate the corresponding word line from a plurality of word lines in the array.

    Double bandwidth algorithmic memory array
    18.
    发明授权
    Double bandwidth algorithmic memory array 有权

    公开(公告)号：US09870163B2

    公开(公告)日：2018-01-16

    申请号：US15140016

    申请日：2016-04-27

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Igor Arsovski ,  Eric D. Hunt-Schroeder ,  Mark W. Kuemerle

    IPC: G06F3/06

    CPC classification number: G06F11/108

    Abstract: The present disclosure relates to memory structures and, more particularly, to double bandwidth algorithmic memory array structures and methods of use. The memory array includes: a plurality of memory banks each of which includes addressable storage units; a redundant array of independent disks (RAID) bank which stores parity bits corresponding to data written into any of the plurality of memory banks at a same address; and a plurality of XOR gates in which data written into any of the plurality of memory banks is cascaded therethrough to refresh the parity bits in the RAID bank.

    Voltage-aware adaptive static random access memory (SRAM) write assist circuit
    19.
    发明授权
    Voltage-aware adaptive static random access memory (SRAM) write assist circuit 有权
    电压感知自适应静态随机存取存储器（SRAM）写辅助电路

    公开(公告)号：US09508420B1

    公开(公告)日：2016-11-29

    申请号：US15009132

    申请日：2016-01-28

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Eric D. Hunt-Schroeder ,  John A. Fifield ,  Darren L. Anand ,  Kevin A. Batson

    IPC: G11C5/14 ,  G11C11/419

    CPC classification number: G11C11/419

    Abstract: Approaches for a write assist circuit are provided. The write assist circuit includes a plurality of binary weighted boost capacitors which each contain a first node coupled to a bitline and a second node connected to a corresponding boost enabling transistor, and a plurality of boost enabling transistors which each contain a gate connected to a boost control enable signal for controlling a corresponding binary weighted boost capacitor. The boost control enable signal of each of the plurality of boost enabling transistors is controlled by encoded values based on a power supply level.

    Abstract translation: 提供写辅助电路的方法。 写辅助电路包括多个二进制加权升压电容器，每个二进制加权升压电容器包含耦合到位线的第一节点和连接到相应升压使能晶体管的第二节点，以及多个升压使能晶体管，每个包含连接到升压器的栅极 用于控制相应的二进制加权升压电容器的控制使能信号。 多个升压启动晶体管中的每一个的升压控制使能信号由基于电源电平的编码值来控制。

Patent Agency Ranking