公开(公告)号：US20170194245A1

公开(公告)日：2017-07-06

申请号：US14987211

申请日：2016-01-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj PATIL ,  Ajey Poovannummoottil JACOB ,  Shesh Mani PANDEY

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/76804 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/5283 ,  H01L28/40

Abstract: A method of providing on-chip capacitance includes providing a starting interconnect structure for semiconductor device(s), the starting interconnect structure including a layer of dielectric material. Vias of a same cross-sectional shape are formed in the layer of dielectric material having different and successive geometric cross-sectional size, and capacitors matching the via shape are formed in the vias. The geometric cross-sectional shapes include circles, squares, hexagons and octagons. For the non-circle shapes, a capacitance thereof is approximated by the capacitance of a coaxial capacitor fitting within and touching all sides of the non-circle shape multiplied by a correction factor of about 0.01 to about 2.

公开(公告)号：US20190371736A1

公开(公告)日：2019-12-05

申请号：US16000174

申请日：2018-06-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil Kumar SINGH ,  Shesh Mani PANDEY

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interconnect structures with reduced capacitance and methods of manufacture. The method includes: forming one or more lower metal lines in a dielectric material; forming an airgap structure in an upper dielectric material above the one or more lower metal lines, by subjecting material to a curing process; and forming an upper metal structure above the airgap structure.

公开(公告)号：US20180337033A1

公开(公告)日：2018-11-22

申请号：US15596437

申请日：2017-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani PANDEY ,  Srikanth Balaji SAMAVEDAM ,  Jui-Hsuan FENG

IPC: H01L21/02

CPC classification number: H01L21/0243 ,  H01L21/02019 ,  H01L21/02381 ,  H01L21/02403 ,  H01L21/02518 ,  H01L21/02658 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/7856

Abstract: Devices and methods of fabricating devices are provided. One method includes: patterning an isolation gate disposed above a trench, the trench extending into a substrate; patterning a gate structure disposed above the substrate and adjacent the isolation gate; depositing a set of sidewall spacers on either side of the isolation gate and gate structure; etching a set of cavities between the isolation gate and gate structure and extending into the substrate; and epitaxially growing a set of epitaxial growths in the set of cavities, wherein the isolation gate is wider than the gate structure, and wherein epitaxial growths adjacent the isolation gate substantially conform to an oxide layer between the isolation gate and the trench, contacting at least a portion of a bottom surface and at least a portion of a side surface of the oxide layer.

公开(公告)号：US20160190252A1

公开(公告)日：2016-06-30

申请号：US14679074

申请日：2015-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peijie FENG ,  Yanxiang LIU ,  Shesh Mani PANDEY ,  Jianwei PENG ,  Francis BENISTANT

IPC: H01L29/08 ,  H01L21/265 ,  H01L29/24 ,  H01L21/3065 ,  H01L21/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/324

CPC classification number: H01L29/41791 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28512 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/785

Abstract: A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET.

Abstract translation: 公开了一种形成具有突然垂直和共形结的源极/漏极区域的方法以及所得到的器件。 实施例包括在第一极性FET的鳍片和第一极性FET的源极/漏极区域上形成第一掩模; 在栅电极的每一侧上在第二极性FET的鳍的相对侧上形成间隔物，第二极性与第一极性相反; 将第一掺杂剂注入到第二极性FET的鳍中; 在栅电极的每一侧蚀刻第二极性FET的鳍的空腔; 去除第一个面罩; 进行快速热退火（RTA）; 在每个空腔中外延生长第二极性FET的源极/漏极区域; 在第一极性FET的鳍片和第一极性FET的源极/漏极区域上形成第二掩模; 以及在所述第二极性FET的源极/漏极区域中注入第二掺杂剂。

公开(公告)号：US20180040516A1

公开(公告)日：2018-02-08

申请号：US15229431

申请日：2016-08-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani PANDEY ,  Baofu ZHU ,  Srikanth Balaji SAMAVEDAM

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/66818 ,  H01L29/7853

Abstract: A method for producing a finFET having a fin with thinned sidewalls on a lower portion above a shallow trench isolation (STI) regions is provided. Embodiments include forming a fin surrounded by STI regions on a substrate; recessing the STI regions, revealing an upper portion of the fin; forming a spacer over side and upper surfaces of the upper portion of the fin; recessing the STI regions, exposing a lower portion of the fin; and thinning sidewalls of the lower portion of the fin.

公开(公告)号：US20160293718A1

公开(公告)日：2016-10-06

申请号：US15180312

申请日：2016-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peijie FENG ,  Yanxiang LIU ,  Shesh Mani PANDEY ,  Jianwei PENG ,  Francis BENISTANT

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/45 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/41791 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28512 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/785

Abstract: A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET.

公开(公告)号：US20160190251A1

公开(公告)日：2016-06-30

申请号：US14676912

申请日：2015-04-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peijie FENG ,  Jianwei PENG ,  Yanxiang LIU ,  Shesh Mani PANDEY ,  Francis BENISTANT

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/24 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H01L29/167

CPC classification number: H01L29/0847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/105 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a source/drain region with an abrupt, vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a gate electrode over and perpendicular to a semiconductor fin; forming first spacers on opposite sides of the gate electrode; forming second spacers on opposite sides of the fin; forming a cavity in the fin adjacent the first spacers, between the second spacers; partially epitaxially growing source/drain regions in each cavity; implanting a first dopant into the partially grown source/drain regions with an optional RTA thereafter; epitaxially growing a remainder of the source/drain regions in the cavities, in situ doped with a second dopant; and implanting a third dopant in the source/drain regions.