公开(公告)号：US20180076022A1

公开(公告)日：2018-03-15

申请号：US15584637

申请日：2017-05-02

申请人： SK hynix Inc.

发明人： Yong Soo CHOI ,  Ho Jin JEONG

IPC分类号： H01L21/02 ,  H01L21/447

CPC分类号： H01L21/02164 ,  B81C1/00952 ,  H01L21/02019 ,  H01L21/02052 ,  H01L21/0206 ,  H01L21/02063 ,  H01L21/02112 ,  H01L21/02172 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02403 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/447

摘要： In a method of treating a semiconductor substrate, a plurality of active regions and a plurality of trench isolation regions are formed by selectively etching the semiconductor substrate. The semiconductor substrate is washed by providing deionized water to the semiconductor substrate. A silicon-based solution is provided to the semiconductor substrate by replacing the deionized water disposed on the semiconductor substrate with the silicon-based solution. A silicon oxide material is formed from the silicon-based solution by performing a heat treatment on the silicon-based solution and the semiconductor substrate. The silicon oxide material fills the trench isolation regions.

公开(公告)号：US20180053856A1

公开(公告)日：2018-02-22

申请号：US15785562

申请日：2017-10-17

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Takahiro SATO ,  Yasutaka NAKAZAWA ,  Takayuki CHO ,  Shunsuke KOSHIOKA ,  Hajime TOKUNAGA ,  Masami JINTYOU

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L27/32 ,  H01L29/10 ,  H01L21/465 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/66 ,  H01L29/06 ,  H01L29/24 ,  G02F1/1362 ,  H01L29/423 ,  H01L29/04 ,  H01L21/306

CPC分类号： H01L29/78696 ,  G02F1/136277 ,  G02F1/1368 ,  H01L21/02365 ,  H01L21/02403 ,  H01L21/02422 ,  H01L21/02551 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/30604 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/3248 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/7869 ,  H01L29/78693

摘要： A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.

公开(公告)号：US09899214B1

公开(公告)日：2018-02-20

申请号：US15620840

申请日：2017-06-13

申请人： NATIONAL TSING HUA UNIVERSITY

发明人： Jenq-Horng Liang ,  Hsu-Sheng Tsai ,  Wei-Yen Woon

IPC分类号： H01L21/00 ,  H01L21/02

CPC分类号： H01L21/02614 ,  H01L21/02403 ,  H01L21/0242 ,  H01L21/02485 ,  H01L21/02568 ,  H01L21/02664 ,  H01L21/02697

摘要： The present disclosure provides a method for fabricating a vertical heterojunction of metal chalcogenides. The method includes steps of providing a multi-layer material, performing an ion implantation and performing an annealing. The multi-layer material has a carrier and a metal layer, in which the metal layer covers the carrier to form an interface. The carrier includes an oxide of a first metal element, and the metal layer includes a second metal element. The step of performing the ion implantation is to inject a chalcogen ion source into the multi-layer material to allow a plurality of chalcogen ions to be implanted in a depth area of the multi-layer material, and the depth area includes the interface. The step of performing the annealing is to form a first metal chalcogenide and a second metal chalcogenide at two sides of the interface, respectively.

公开(公告)号：US09691715B2

公开(公告)日：2017-06-27

申请号：US15093350

申请日：2016-04-07

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Karthik Balakrishnan ,  Isaac Lauer ,  Tenko Yamashita ,  Jeffrey W. Sleight

IPC分类号： H01L21/02 ,  H01L23/00 ,  H01L29/775 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L23/562 ,  B82Y10/00 ,  H01L21/02403 ,  H01L21/02603 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696

摘要： A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.

公开(公告)号：US09647128B2

公开(公告)日：2017-05-09

申请号：US14505004

申请日：2014-10-02

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki ,  Yasuharu Hosaka ,  Toshimitsu Obonai ,  Junichi Koezuka ,  Yukinori Shima ,  Masahiko Hayakawa ,  Takashi Hamochi ,  Suzunosuke Hiraishi

IPC分类号： H01L29/786 ,  H01L29/24

CPC分类号： H01L21/477 ,  H01L21/02112 ,  H01L21/02403 ,  H01L21/28 ,  H01L29/24 ,  H01L29/78606 ,  H01L29/7869

摘要： To suppress a change in electrical characteristics and to improve reliability in a semiconductor device using a transistor including an oxide semiconductor. The semiconductor device includes a gate electrode over an insulating surface, an oxide semiconductor film overlapping with the gate electrode, a gate insulating film which is between the gate electrode and the oxide semiconductor film and is in contact with a surface of the oxide semiconductor film, a protective film in contact with an opposite surface of the surface of the oxide semiconductor film, and a pair of electrodes in contact with the oxide semiconductor film. In the gate insulating film or the protective film, the amount of gas having a mass-to-charge ratio m/z of 17 released by heat treatment is greater than the amount of nitrogen oxide released by heat treatment.

公开(公告)号：US09627330B2

公开(公告)日：2017-04-18

申请号：US14798007

申请日：2015-07-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Karthik Balakrishnan ,  Isaac Lauer ,  Tenko Yamashita ,  Jeffrey W. Sleight

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L23/00 ,  H01L29/775 ,  H01L29/786 ,  H01L29/66

CPC分类号： H01L23/562 ,  B82Y10/00 ,  H01L21/02403 ,  H01L21/02603 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696

摘要： A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.

公开(公告)号：US20150171220A1

公开(公告)日：2015-06-18

申请号：US14404046

申请日：2013-04-26

申请人： Sharp Kabushiki Kaisha

发明人： Kazuhide Tomiyasu

IPC分类号： H01L29/786 ,  H01L21/477 ,  H01L21/02 ,  H01L29/45 ,  H01L29/66

CPC分类号： H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02403 ,  H01L21/477 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

摘要： This semiconductor device (100) includes a substrate (10) and a TFT which is provided on the substrate. The TFT includes a gate electrode (12), an oxide semiconductor layer (14) which faces the gate electrode, source and drain electrodes (16, 18) which are connected to the oxide semiconductor layer, and an insulating layer (22) which contacts at least partially with the source and drain electrodes. The insulating layer (22) includes a lower region (22b) which contacts at least partially with the source and drain electrodes and an upper region (22a) which is located over the lower region. The lower region (22b) has a higher hydrogen content than the upper region (22a).

摘要翻译： 该半导体器件（100）包括衬底（10）和设置在衬底上的TFT。 TFT包括栅电极（12），面对栅电极的氧化物半导体层（14），连接到氧化物半导体层的源极和漏极（16,18）以及与氧化物半导体层相连的绝缘层（22） 至少部分地具有源极和漏极。 绝缘层（22）包括至少部分地与源极和漏极接触的下部区域（22b）和位于下部区域上方的上部区域（22a）。 下部区域（22b）的氢含量比上部区域（22a）高。

公开(公告)号：US08871119B2

公开(公告)日：2014-10-28

申请号：US13729535

申请日：2012-12-28

申请人： Idemitsu Kosan Co., Ltd.

发明人： Koki Yano ,  Hirokazu Kawashima

IPC分类号： H01B1/02 ,  H01L29/22 ,  C23C14/34 ,  H01L29/786 ,  C04B35/453 ,  H01L21/02

CPC分类号： H01L29/2206 ,  C04B35/453 ,  C23C14/3414 ,  H01L21/02403 ,  H01L21/02422 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/02631 ,  H01L29/7869 ,  H01L29/78693 ,  Y10T428/10

摘要： A composite oxide sintered body includes In, Zn, and Sn, and has a relative density of 90% or more, an average crystal grain size of 10 μm or less, and a bulk resistance of 30 mΩcm or less, the number of tin oxide aggregate particles having a diameter of 10 μm or more being 2.5 or less per mm2 of the composite oxide sintered body.

摘要翻译： 复合氧化物烧结体包括In，Zn和Sn，相对密度为90％以上，平均结晶粒径为10μm以下，体积电阻为30mΩ，OHgr·cm以下， 直径为10μm以上的氧化锡骨料粒子为复合氧化物烧结体的每mm 2为2.5以下。

公开(公告)号：US08735195B2

公开(公告)日：2014-05-27

申请号：US12756278

申请日：2010-04-08

申请人： Naochika Horio

发明人： Naochika Horio

IPC分类号： H01L33/28 ,  H01L33/36 ,  H01L33/38 ,  H01L33/42

CPC分类号： H01L33/36 ,  H01L21/02403 ,  H01L21/02433 ,  H01L21/02472 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02573 ,  H01L33/0083 ,  H01L33/28 ,  H01L33/38 ,  H01L33/42

摘要： Disclosed is a method of manufacturing a ZnO-based semiconductor device having at least p-type ZnO-based semiconductor layer, which includes a step of forming a contact metal layer on the p-type ZnO-based semiconductor layer wherein the contact metal layer contains at least one of Ni and Cu; and a step of performing heat treatment of the contact metal layer and the p-type ZnO-based semiconductor layer under an oxygen-free atmosphere to form a mixture layer including elements of the p-type ZnO-based semiconductor layer and the contact metal layer at a boundary region therebetween while maintaining a metal phase layer on a surface of the contact metal layer.

摘要翻译： 公开了一种制造至少具有p型ZnO类半导体层的ZnO类半导体器件的方法，其包括在p型ZnO基半导体层上形成接触金属层的步骤，其中接触金属层含有 Ni和Cu中的至少一种; 以及在无氧气氛下对接触金属层和p型ZnO类半导体层进行热处理以形成包含p型ZnO类半导体层和接触金属层的元素的混合层的工序 在其间的边界区域，同时在接触金属层的表面上保持金属相层。

公开(公告)号：US20140138674A1

公开(公告)日：2014-05-22

申请号：US14073993

申请日：2013-11-07

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Takahiro SATO ,  Yasutaka NAKAZAWA ,  Takayuki CHO ,  Shunsuke KOSHIOKA ,  Hajime TOKUNAGA ,  Masami JINTYOU

IPC分类号： H01L29/786

CPC分类号： H01L29/7869 ,  G02F1/136277 ,  G02F1/1368 ,  H01L21/02365 ,  H01L21/02403 ,  H01L21/02422 ,  H01L21/02551 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/30604 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/3248 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78693 ,  H01L29/78696

摘要： A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.

摘要翻译： 晶体管包括层叠有氧化物半导体膜和氧化膜的多层膜，栅极电极和栅极绝缘膜。 多层膜与栅电极重叠，栅极绝缘膜插入其间。 多层膜具有在氧化物半导体膜的底面和氧化物半导体膜的侧面之间具有第一角度的形状，以及氧化物膜的底面与氧化膜的侧面之间的第二角度。 第一个角度是锐角并小于第二个角度。 此外，制造包括这种晶体管的半导体器件。