公开(公告)号：US09500703B2

公开(公告)日：2016-11-22

申请号：US14462643

申请日：2014-08-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anil Kumar ,  Suresh Uppal ,  Manjunatha Prabhu ,  William McMahon

IPC: G01R31/26 ,  G01R31/28

CPC classification number: G01R31/2884 ,  G01R31/2601 ,  G01R31/2644 ,  H01L22/34

Abstract: There is set forth herein a semiconductor structure including a plurality of test devices, the plurality of test devices including a first test device and a second test device. A semiconductor structure can also include a waveform generating circuit, the waveform generating circuit configured for application of a first stress signal waveform having a first duty cycle to the first test device, and a second stress signal waveform having a second duty cycle to the second test device. A semiconductor structure can include a selection circuit associated with each of the first test device and the second test device for switching between a stress cycle and a sensing cycle.

Abstract translation: 这里提出了包括多个测试装置的半导体结构，所述多个测试装置包括第一测试装置和第二测试装置。 半导体结构还可以包括波形发生电路，波形发生电路被配置为将第一应力信号波形具有第一占空比施加到第一测试装置，第二应力信号波形具有第二占空比到第二测试 设备。 半导体结构可以包括与第一测试装置和第二测试装置中的每一个相关联的选择电路，用于在应力循环和感测周期之间切换。

公开(公告)号：US09916212B2

公开(公告)日：2018-03-13

申请号：US15047395

申请日：2016-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Randy W. Mann ,  William McMahon ,  Yoann Mamy Randriamihaja ,  Yuncheng Song

IPC: G06F11/00 ,  G06F11/16 ,  G06F11/20

CPC classification number: G06F11/167 ,  G06F11/2015 ,  G06F2201/85 ,  G11C7/04 ,  G11C11/419 ,  G11C29/00 ,  G11C29/028 ,  G11C29/52

Abstract: Method, apparatus, and system for improving semiconductor device writeability at row/bit level through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS, wherein the first array supply voltage and the second array supply voltage are greater than the operational array supply voltage. By virtue of BTI, application of the first array supply voltage may lead to improved writeability of one or more cells of the device.

公开(公告)号：US20170292986A1

公开(公告)日：2017-10-12

申请号：US15625609

申请日：2017-06-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Suresh Uppal ,  Andreas Kerber ,  William McMahon

IPC: G01R31/12 ,  G01R31/26 ,  G01R31/28

CPC classification number: G01R31/129 ,  G01R31/2607 ,  G01R31/2623 ,  G01R31/2642 ,  G01R31/2874

Abstract: At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on a device. A device having at least one transistor and at least one dielectric layer is provided. A test signal is provided for performing a TDDB test and a BTI test on the device. The TDDB test and the BTI test are performed substantially simultaneously on the device based upon the test signal. The data relating to a breakdown of the dielectric layer and at least one characteristic of the transistor based upon the TDDB test and the BTI test is acquired, stored, and/or transmitted.

公开(公告)号：US09702926B2

公开(公告)日：2017-07-11

申请号：US14288278

申请日：2014-05-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suresh Uppal ,  Andreas Kerber ,  William McMahon

IPC: G01R31/26 ,  G01R31/12

CPC classification number: G01R31/129 ,  G01R31/2607 ,  G01R31/2623 ,  G01R31/2642 ,  G01R31/2874

Abstract: At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on a device. A device having at least one transistor and at least one dielectric layer is provided. A test signal is provided for performing a TDDB test and a BTI test on the device. The TDDB test and the BTI test are performed substantially simultaneously on the device based upon the test signal. The data relating to a breakdown of the dielectric layer and at least one characteristic of the transistor based upon the TDDB test and the BTI test is acquired, stored, and/or transmitted.

公开(公告)号：US09601188B1

公开(公告)日：2017-03-21

申请号：US15047139

申请日：2016-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Randy W. Mann ,  William McMahon ,  Yoann Mamy Randriamihaja ,  Yuncheng Song

IPC: G11C11/00 ,  G11C11/419

CPC classification number: G11C29/70 ,  G11C7/04 ,  G11C8/08 ,  G11C11/418 ,  G11C29/56

Abstract: We disclose methods, apparatus, and systems for improving semiconductor device yield and/or reliability through bias temperature instability (BTI). One device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line controls access to each pass gate of a first number of cells; a word line driver electrically connected to each word line; a row decoder configured to authorize or deauthorize a write voltage to each word line through the word line driver, wherein the write voltage is selected from an operational write voltage or a first write voltage; and a control line configured to provide an operational write voltage or a first write voltage to each word line authorized by the row decoder, wherein the first write voltage is greater than an operational write voltage.

公开(公告)号：US09372226B2

公开(公告)日：2016-06-21

申请号：US14337290

申请日：2014-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suresh Uppal ,  Randy W. Mann ,  William McMahon

IPC: G06F17/00 ,  G01R31/28 ,  H01L23/525 ,  H01L21/66

CPC classification number: G01R31/2884 ,  G01R31/2644 ,  H01L22/14 ,  H01L22/34 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Wafer test structures and methods of providing wafer test structures are described. The methods include: fabricating multiple test devices and multiple fuse devices on the wafer, each test device having a respective fuse device associated therewith, which open circuits upon failure of the test device; and fabricating a selection circuit operative to selectively connect one test device to a sense contact pad, and the other test devices to a stress contact pad. The selection circuit facilitates sensing one or more electrical signals of the one test device by electrical contact with the sense contact pad, while stress testing the other test devices by electrical contact with the stress contact pad. In one embodiment, each test device has respective first and second switch devices, operative to selectively electrically connect the test device to the sense or stress contact pads. In another embodiment, the method includes wafer testing using the test structure.

Abstract translation: 描述了晶片测试结构和提供晶片测试结构的方法。 这些方法包括：在晶片上制造多个测试装置和多个保险丝装置，每个测试装置具有与其相关联的相应的熔丝装置，其在测试装置故障时断开电路; 以及制造选择电路，其操作以选择性地将一个测试装置连接到感测触点焊盘，并且将其它测试装置连接到应力接触焊盘。 选择电路通过与感测接触焊盘的电接触便于感测一个测试装置的一个或多个电信号，同时通过与应力接触焊盘电接触来测试其它测试装置。 在一个实施例中，每个测试装置具有相应的第一和第二开关装置，其可操作以选择性地将测试装置电连接到感测或应力接触垫。 在另一个实施例中，该方法包括使用测试结构的晶片测试。