公开(公告)号：US09613898B2

公开(公告)日：2017-04-04

申请号：US14838554

申请日：2015-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andreas Kurz ,  Andrei Sidelnicov

IPC: H01L23/525 ,  H01L27/12 ,  H01L21/84 ,  H01L29/417 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66 ,  H01L23/532 ,  H01L29/16

CPC classification number: H01L23/5256 ,  H01L21/02532 ,  H01L21/76264 ,  H01L21/84 ,  H01L23/53209 ,  H01L27/1203 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41783 ,  H01L29/66515 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7838

Abstract: A method of manufacturing a semiconductor device with a fuse is provided including the steps of providing a semiconductor-on-insulator (SOI) structure including an insulating layer and a semiconductor layer formed on the insulating layer, forming a first raised semiconductor region on the semiconductor layer and a second raised semiconductor region on the semiconductor layer adjacent to the first semiconductor region, and performing a silicidation process of the first and second raised semiconductor regions to form a first at least partially silicided raised semiconductor region with a first silicided portion and a second at least partially silicided raised semiconductor region with a second silicided portion.

公开(公告)号：US20170062333A1

公开(公告)日：2017-03-02

申请号：US14838554

申请日：2015-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andreas Kurz ,  Andrei Sidelnicov

IPC: H01L23/525 ,  H01L21/84 ,  H01L29/417 ,  H01L29/16 ,  H01L21/762 ,  H01L29/66 ,  H01L23/532 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L23/5256 ,  H01L21/02532 ,  H01L21/76264 ,  H01L21/84 ,  H01L23/53209 ,  H01L27/1203 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41783 ,  H01L29/66515 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7838

Abstract: A method of manufacturing a semiconductor device with a fuse is provided including the steps of providing a semiconductor-on-insulator (SOI) structure including an insulating layer and a semiconductor layer formed on the insulating layer, forming a first raised semiconductor region on the semiconductor layer and a second raised semiconductor region on the semiconductor layer adjacent to the first semiconductor region, and performing a silicidation process of the first and second raised semiconductor regions to form a first at least partially silicided raised semiconductor region with a first silicided portion and a second at least partially silicided raised semiconductor region with a second silicided portion.

Abstract translation: 提供一种制造具有熔丝的半导体器件的方法，包括以下步骤：提供绝缘层上绝缘体（SOI）结构，其中绝缘层和半导体层形成在绝缘层上，在半导体上形成第一凸起半导体区域 层和与所述第一半导体区域相邻的所述半导体层上的第二凸起半导体区域，以及执行所述第一和第二凸起半导体区域的硅化处理，以形成具有第一硅化部分和第二半导体区域的第一至少部分硅化凸起的半导体区域 至少部分硅化凸起的半导体区域，具有第二硅化部分。

公开(公告)号：US20160141393A1

公开(公告)日：2016-05-19

申请号：US15003370

申请日：2016-01-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Andreas Kurz ,  Sven Beyer ,  Wolfgang Buchholtz

IPC: H01L29/66 ,  H01L21/308 ,  H01L49/02 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/308 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/0738 ,  H01L28/20 ,  H01L29/66545

Abstract: A method includes forming a plurality of fins in a semiconductor substrate using a common patterning process. A conductive layer is formed above the plurality of fins. A mask is formed above the conductive layer. The conductive layer is etched using the mask to define trenches in the conductive layer. A first insulating layer is formed above the conductive layer and in the trenches. First and second contacts are formed connected to respective ends of the conductive layer.

Abstract translation: 一种方法包括使用共同的图案化工艺在半导体衬底中形成多个翅片。 在多个翅片上方形成导电层。 在导电层上方形成掩模。 使用掩模蚀刻导电层以在导电层中限定沟槽。 第一绝缘层形成在导电层上方和沟槽中。 第一和第二触点形成为连接到导电层的相应末端。

公开(公告)号：US20150179632A1

公开(公告)日：2015-06-25

申请号：US14136581

申请日：2013-12-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andrei Sidelnicov ,  Andreas Kurz ,  Alexandru Romanescu

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/49 ,  H01L23/525

CPC classification number: H01L27/0629 ,  H01L23/5256 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor device including the steps of forming an electrically programmable fuse (e-fuse) on an isolation region and a transistor on an active region of a wafer, wherein forming the transistor includes forming a dummy gate above a substrate, removing the dummy gate and forming a metal gate in place of the dummy gate, and forming the e-fuse includes forming a metal-containing layer above the isolation region, forming a semiconductor layer on the metal-containing layer during the process of forming the dummy gate and of the same material as the dummy gate, forming a hard mask layer on the semiconductor layer formed on the metal-containing layer, and forming contact openings in the hard mask layer and semiconductor layer during the process of removing the dummy gate.

Abstract translation: 一种形成半导体器件的方法，包括以下步骤：在隔离区域上形成电可编程熔丝（e-fuse）和在晶片的有源区上形成晶体管，其中形成晶体管包括在衬底上形成虚拟栅极，去除 虚拟栅极和形成金属栅极代替虚拟栅极，并且形成e熔丝包括在隔离区域上方形成含金属层，在形成虚拟栅极的过程中在含金属层上形成半导体层 栅极和与虚拟栅极相同的材料，在形成在含金属层上的半导体层上形成硬掩模层，并且在去除虚拟栅极的过程中在硬掩模层和半导体层中形成接触开口。