公开(公告)号：US09633962B2

公开(公告)日：2017-04-25

申请号：US14048483

申请日：2013-10-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Ekta Misra ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L21/44 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L24/11 ,  H01L21/7684 ,  H01L21/76877 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03602 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05655 ,  H01L2224/11 ,  H01L2224/11009 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/014

Abstract: Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. Via openings extend through the passivation layer from a top surface of the passivation layer to a metal line in the passivation layer. A conductive layer is formed on the top surface of the passivation layer and within each via opening. When the passivation layer and the conductive layer are planarized, a plug is formed that includes sections in the via openings. Each section is coupled with the metal line.

公开(公告)号：US09466547B1

公开(公告)日：2016-10-11

申请号：US14734600

申请日：2015-06-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/54

CPC classification number: H01L23/3171 ,  H01L21/4853 ,  H01L21/563 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/364 ,  H01L2224/11 ,  H01L2224/03

Abstract: A topographical structure is formed within an integrated circuit (IC) chip passivation layer. The topographical structure includes a trench extending below the top surface of the passivation layer and above the top surface of an uppermost inter-metallic dielectric layer underlying the passivation layer associated with the uppermost wiring line of the IC chip. The topographical structure may also include a ridge above the top surface of the passivation layer along the perimeter of the trench. The topographical structure may be positioned between a series of IC chip contact pads and/or may be positioned around a particular IC chip contact pad. The topographical structures increase the surface area of the passivation layer resulting in increased underfill bonding to the passivation layer. The topographical structures also influence capillary movement of capillary underfill and may be positioned to speed up, slow down, or divert the movement of the capillary underfill.

Abstract translation: 在集成电路（IC）芯片钝化层内形成一种形貌结构。 形貌结构包括在钝化层的顶表面下方延伸的沟槽，并且在与IC芯片的最上面布线相关联的钝化层下面的最上面的金属间介电层的顶表面之上。 形貌结构还可以包括沿着沟槽的周边的钝化层的顶表面上方的脊。 形状结构可以位于一系列IC芯片接触焊盘之间和/或可以位于特定的IC芯片接触焊盘周围。 形貌结构增加了钝化层的表面积，从而增加了与钝化层的底部填充结合。 地形结构还影响毛细管底部填充物的毛细管运动，并且可以定位成加速，减慢或转移毛细管底部填充物的移动。

公开(公告)号：US10049897B2

公开(公告)日：2018-08-14

申请号：US15421737

申请日：2017-02-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L21/306 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, an interconnect structure can include: a photosensitive polyimide (PSPI) layer including a pedestal portion; a controlled collapse chip connection (C4) bump overlying the pedestal portion of the PSPI layer; a solder overlying the C4 bump and contacting a side of the C4 bump; and an underfill layer abutting the pedestal portion of the PSPI and the C4 bump, wherein the underfill layer and the solder form a first interface separated from the PSPI pedestal.