Patent search cpc:"H01L2224/03602" Page 1

1.

发明申请
METHOD FOR IMPROVING WIRE BONDING STRENGTH OF AN IMAGE SENSOR 审中-公开

公开(公告)号：US20180096958A1

公开(公告)日：2018-04-05

申请号：US15663531

申请日：2017-07-28

Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION , SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION

Inventor： YUNLONG KONG

IPC: H01L23/00 , H01L27/146 , H04N5/369

CPC classification number: H01L24/05 , H01L23/3171 , H01L24/03 , H01L27/14621 , H01L27/14623 , H01L27/14634 , H01L27/14636 , H01L27/14643 , H01L27/14645 , H01L27/14685 , H01L27/1469 , H01L2224/0212 , H01L2224/034 , H01L2224/03602 , H01L2224/03616 , H01L2224/05093 , H01L2224/05098 , H01L2224/05124 , H01L2224/05147 , H01L2224/05624 , H01L2224/48227 , H01L2224/73265 , H04N5/369 , H01L2924/00014

Abstract: A method for manufacturing a bond pad structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, and a passivation layer on the first metal layer, the passivation layer having an opening extending to the first metal layer; and filling the opening of the passivation layer with a second metal layer. The bond pad structure has a significantly increased thickness compared with the thickness of the exposed portion of the first metal layer in the opening, thereby ensuring wire bonding reliability and yield.

2.

发明授权
Semiconductor apparatus, solid state imaging device, imaging apparatus and electronic equipment, and manufacturing method thereof 有权

公开(公告)号：US09881962B2

公开(公告)日：2018-01-30

申请号：US15035839

申请日：2014-11-27

Applicant: SONY CORPORATION

Inventor： Hidetsugu Otani , Yuuji Kishigami

IPC: H01L27/14 , H01L27/146 , H04N5/225 , H01L23/00

CPC classification number: H01L27/14643 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L27/14618 , H01L27/14636 , H01L27/14683 , H01L27/14689 , H01L2224/02371 , H01L2224/0346 , H01L2224/03602 , H01L2224/0401 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/06182 , H01L2224/131 , H01L2224/16057 , H01L2224/16105 , H01L2224/16227 , H01L2224/94 , H04N5/2253 , H04N5/2254 , H01L2924/014 , H01L2224/03 , H01L2924/00014

Abstract: The present technology relates to a semiconductor apparatus, a solid state imaging device, an imaging apparatus and electronic equipment which realize a smaller and thinner size and which enable improvement of optical characteristics, and a manufacturing method thereof. A side electrode 16c is formed on a side face of a substrate on which an imaging device 16 is formed. By this side electrode 16c being connected to an electrode pad 15b on the substrate 15 through a chip wiring 17 formed with solder, the imaging device 16 is electrically connected to the substrate 15. By this means, because it is possible to electrically connect the imaging device 16 to the substrate 15 without using wire bonding, space required for wire bonding is not required, so that it is possible to realize a smaller and thinner apparatus. The present technology can be applied to an imaging apparatus.

3.

发明申请
Semiconductor Device and Method of Forming Conductive Vias by Direct Via Reveal with Organic Passivation 审中-公开

公开(公告)号：US20170365517A1

公开(公告)日：2017-12-21

申请号：US15675556

申请日：2017-08-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Xing Zhao , Duk Ju Na , Lai Yee Chia

IPC: H01L21/768 , H01L23/00 , H01L25/065 , H01L23/48 , H01L21/66

CPC classification number: H01L21/76898 , H01L22/14 , H01L23/291 , H01L23/293 , H01L23/3192 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/10 , H01L24/13 , H01L24/81 , H01L24/94 , H01L25/0657 , H01L2224/03002 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/03602 , H01L2224/03616 , H01L2224/0391 , H01L2224/0401 , H01L2224/05562 , H01L2224/0557 , H01L2224/05571 , H01L2224/05572 , H01L2224/05573 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05681 , H01L2224/05684 , H01L2224/06181 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11849 , H01L2224/13023 , H01L2224/13025 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16013 , H01L2224/16014 , H01L2224/16145 , H01L2224/16146 , H01L2224/81191 , H01L2224/81815 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2924/13091

Abstract: A semiconductor device has a semiconductor wafer and a conductive via formed partially through the semiconductor wafer. A portion of the semiconductor wafer and conductive via is removed by a chemical mechanical polishing process. The semiconductor wafer and conductive via are coplanar at first and second surfaces. A first insulating layer and a second insulating layer are formed over the conductive via and semiconductor wafer. The first insulating layer includes an inorganic material and the second insulating layer includes an organic material. An opening in the first and second insulating layers is formed over the conductive via while a second portion of the conductive via remains covered by the first and second insulating layers. A conductive layer is formed over the conductive via and first insulating layer. An interconnect structure is formed over the conductive layer. The semiconductor wafer is singulated into individual semiconductor die.

4.

发明授权
Method of manufacturing an electronic device having a contact pad with partially sealed pores 有权

公开(公告)号：US09620466B1

公开(公告)日：2017-04-11

申请号：US14953456

申请日：2015-11-30

Applicant: Infineon Technologies AG

Inventor： Martin Mischitz , Markus Heinrici , Barbara Eichinger , Manfred Schneegans , Stefan Krivec

IPC: H01L21/00 , H01L23/00 , H01L21/02 , H01L23/532

CPC classification number: H01L24/03 , H01L21/02203 , H01L21/02513 , H01L21/76259 , H01L23/53238 , H01L24/05 , H01L2224/0331 , H01L2224/0345 , H01L2224/03505 , H01L2224/03602 , H01L2224/03616 , H01L2224/0384 , H01L2224/05541 , H01L2224/05551 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2924/3511 , H01L2924/35121

Abstract: A method of manufacturing an electronic device may include: forming at least one electronic component in a substrate; forming a contact pad in electrical contact with the at least one electronic component; wherein forming the contact pad includes: forming a first layer over the substrate; planarizing the first layer to form a planarized surface of the first layer; and forming a second layer over the planarized surface, wherein the second layer has a lower porosity than the first layer.

5.

发明授权
Wafer to wafer bonding process and structures 有权

公开(公告)号：US09613926B2

公开(公告)日：2017-04-04

申请号：US14712729

申请日：2015-05-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu , Ming-Fa Chen , Wen-Ching Tsai

IPC: H01L23/00 , B81C3/00 , H01L23/10 , H01L21/50

CPC classification number: H01L24/81 , B81C1/00238 , B81C3/001 , B81C2203/031 , B81C2203/035 , H01L21/50 , H01L23/10 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/80 , H01L24/83 , H01L24/92 , H01L24/94 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/03602 , H01L2224/03614 , H01L2224/03616 , H01L2224/03912 , H01L2224/0401 , H01L2224/04026 , H01L2224/05022 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05149 , H01L2224/05155 , H01L2224/05166 , H01L2224/05184 , H01L2224/05548 , H01L2224/05567 , H01L2224/05569 , H01L2224/05571 , H01L2224/056 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05684 , H01L2224/06051 , H01L2224/08225 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11614 , H01L2224/119 , H01L2224/11912 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13149 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/16014 , H01L2224/16147 , H01L2224/2745 , H01L2224/27452 , H01L2224/27462 , H01L2224/27464 , H01L2224/2747 , H01L2224/27614 , H01L2224/279 , H01L2224/27912 , H01L2224/29011 , H01L2224/29013 , H01L2224/29014 , H01L2224/29082 , H01L2224/291 , H01L2224/29111 , H01L2224/29124 , H01L2224/29138 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29149 , H01L2224/29155 , H01L2224/29164 , H01L2224/29166 , H01L2224/32014 , H01L2224/32147 , H01L2224/32225 , H01L2224/73103 , H01L2224/80805 , H01L2224/80893 , H01L2224/80894 , H01L2224/80895 , H01L2224/80896 , H01L2224/81815 , H01L2224/8183 , H01L2224/83805 , H01L2224/83815 , H01L2224/8383 , H01L2224/92 , H01L2224/9202 , H01L2224/94 , H01L2924/10158 , H01L2924/1461 , H01L2924/163 , H01L2924/00014 , H01L2924/01014 , H01L2224/03 , H01L2224/11 , H01L2224/27 , H01L2924/00012 , H01L2224/0347 , H01L2924/014 , H01L2224/81 , H01L2224/83 , H01L2224/114 , H01L2224/1146 , H01L2224/1161 , H01L2224/274 , H01L2224/2746 , H01L2224/2761 , H01L21/302 , H01L2224/034 , H01L2224/0361 , H01L2224/80

Abstract: Bonded structures and method of forming the same are provided. A conductive layer is formed on a first surface of a bonded structure, the bonded structure including a first substrate bonded to a second substrate, the first surface of the bonded structure being an exposed surface of the first substrate. A patterned mask having first openings and second openings is formed on the conductive layer, the first openings and the second openings exposing portions of the conductive layer. First portions of first bonding connectors are formed in the first openings and first portions of second bonding connectors are formed in the second openings. The conductive layer is patterned to form second portions of the first bonding connectors and second portions of the second bonding connectors. The bonded structure is bonded to a third substrate using the first bonding connectors and the second bonding connectors.

6.

发明申请
CONDUCTIVE STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
Title translation: 导电结构及其形成方法

公开(公告)号：US20150011082A1

公开(公告)日：2015-01-08

申请号：US14494026

申请日：2014-09-23

Applicant: CHIPMOS TECHNOLOGIES INC.

Inventor： Geng-Shin SHEN , Chung-Pang CHI

IPC: H01L23/00

CPC classification number: H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/034 , H01L2224/03602 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05073 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05172 , H01L2224/05184 , H01L2224/05571 , H01L2224/05573 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/1132 , H01L2224/11462 , H01L2224/1148 , H01L2224/11831 , H01L2224/1184 , H01L2224/11845 , H01L2224/13022 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/1329 , H01L2224/133 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/00012 , H01L2224/05552

Abstract: A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a semiconductor substrate, a pad, a passivation layer and a patterned insulating layer. The patterned insulating layer is disposed on the passivation layer and partially and directly covers the first opening of the pad to expose a second opening. The conductive structure comprises an under bump metal (UBM) layer and a conductive bump. The UBM layer is disposed in the second opening defined by the patterned insulating layer and is electrically connected to the pad. The conductive bump is disposed on the UBM layer and is electrically connected to the UBM layer. The upper surface of the conductive bump is greater than the upper surface of the patterned insulating layer, while the portion of the conductive bump disposed in the second opening is covered by the UBM layer.

Abstract translation: 提供了一种用于半导体芯片的导电结构和用于形成导电结构的方法。半导体芯片包括半导体衬底，衬垫，钝化层和图案化绝缘层。图案化的绝缘层设置在钝化层上，并且部分地并且直接覆盖焊盘的第一开口以露出第二开口。导电结构包括凹凸金属（UBM）层和导电凸块。 UBM层设置在由图案化的绝缘层限定的第二开口中，并且电连接到焊盘。导电凸块设置在UBM层上并与UBM层电连接。导电凸块的上表面大于图案化绝缘层的上表面，而布置在第二开口中的导电凸块的部分被UBM层覆盖。

7.

发明申请
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 审中-公开
Title translation: 半导体器件及其形成方法

公开(公告)号：US20130260551A1

公开(公告)日：2013-10-03

申请号：US13903164

申请日：2013-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-Byoung Kang , Kwang-chul Choi , Jung-Hwan Kim , Tae Hong Min , Hojin Lee , Minseung Yoon

IPC: H01L21/48

CPC classification number: H01L21/4835 , H01L21/6836 , H01L21/76898 , H01L23/3114 , H01L23/3192 , H01L23/49827 , H01L24/06 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L27/14618 , H01L2221/68327 , H01L2221/6834 , H01L2224/02166 , H01L2224/02313 , H01L2224/02372 , H01L2224/02375 , H01L2224/02381 , H01L2224/024 , H01L2224/03462 , H01L2224/03466 , H01L2224/03602 , H01L2224/0401 , H01L2224/04042 , H01L2224/05008 , H01L2224/05022 , H01L2224/05026 , H01L2224/05147 , H01L2224/05548 , H01L2224/05567 , H01L2224/05571 , H01L2224/05647 , H01L2224/06131 , H01L2224/06135 , H01L2224/06138 , H01L2224/06181 , H01L2224/13007 , H01L2224/13022 , H01L2224/13024 , H01L2224/13025 , H01L2224/16147 , H01L2224/16225 , H01L2224/16227 , H01L2224/29011 , H01L2224/32225 , H01L2224/45139 , H01L2224/48105 , H01L2224/48227 , H01L2224/48228 , H01L2224/73253 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/05552 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012

Abstract: In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern. Therefore, a semiconductor device with enhanced reliability may be implemented.

Abstract translation: 在半导体器件中，有机绝缘图案设置在第一和第二重新布线图案之间。有机绝缘图案可以吸收当第一和第二重新布线图案在加热下膨胀时发生的物理应力。由于有机绝缘图案设置在第一和第二重新布线图案之间，所以可以相对于其中在重新布线图案之间设置半导体图案的半导体器件来增加绝缘性能。此外，由于在第一和第二重新布线图案和有机绝缘图案之间以及基板和有机绝缘图案之间设置种子层图案，所以第一和第二布线图案的粘合强度提高。这也减少了分层问题。此外，种子层图案防止形成重新布线图案的金属扩散到有机绝缘图案。因此，可以实现具有增强的可靠性的半导体器件。

8.

发明申请
DEVICE AND METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE 有权
Title translation: 用于制造电子设备的装置和方法

公开(公告)号：US20130168870A1

公开(公告)日：2013-07-04

申请号：US13340770

申请日：2011-12-30

Applicant: Edward Fuergut , Joachim Mahler

Inventor： Edward Fuergut , Joachim Mahler

IPC: H01L21/56 , H01L23/522

CPC classification number: H01L23/49517 , H01L21/4832 , H01L21/561 , H01L21/568 , H01L23/3107 , H01L23/49562 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/24 , H01L24/96 , H01L24/97 , H01L2224/02372 , H01L2224/02379 , H01L2224/03003 , H01L2224/03438 , H01L2224/0344 , H01L2224/03602 , H01L2224/0361 , H01L2224/04105 , H01L2224/05026 , H01L2224/051 , H01L2224/05571 , H01L2224/96 , H01L2224/97 , H01L2924/00014 , H01L2924/10253 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2224/03 , H01L2924/00012 , H01L2924/014 , H01L2224/05552

Abstract: A method for manufacturing an electronic interconnect device is described, the method comprising: providing an electronic members each having one or more electrical contacts on a first member side thereof; providing a carrier having a carrier base and having sets of one or more electrically conductive projections on a surface of the carrier base; attaching the electronic members with the corresponding contacts thereof to the respective set of projections to thereby electrically connect the one or more electrical contacts of the respective chip with the corresponding one or more electrically conductive projections of the respective set; encapsulating exposed portions of the electronic member with an encapsulating material to form an encapsulation.

Abstract translation: 描述了一种用于制造电子互连器件的方法，所述方法包括：在其第一部件侧上提供每个具有一个或多个电触点的电子部件; 提供具有载体基底并且在载体基底的表面上具有一组或多个导电突起的载体; 将具有其相应触点的电子部件附接到相应的一组突起，从而将相应芯片的一个或多个电触点与相应组的相应的一个或多个导电突起电连接; 用封装材料封装电子部件的暴露部分以形成封装。