公开(公告)号：US09633962B2

公开(公告)日：2017-04-25

申请号：US14048483

申请日：2013-10-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Ekta Misra ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L21/44 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L24/11 ,  H01L21/7684 ,  H01L21/76877 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03602 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05655 ,  H01L2224/11 ,  H01L2224/11009 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/014

Abstract: Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. Via openings extend through the passivation layer from a top surface of the passivation layer to a metal line in the passivation layer. A conductive layer is formed on the top surface of the passivation layer and within each via opening. When the passivation layer and the conductive layer are planarized, a plug is formed that includes sections in the via openings. Each section is coupled with the metal line.

公开(公告)号：US10096557B2

公开(公告)日：2018-10-09

申请号：US15791568

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ekta Misra ,  Mukta G. Farooq ,  Krishna Tunga

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L21/3205

Abstract: Structure and method for reducing thermal-mechanical stresses generated for a semiconductor device are provided, which includes a tiled-stress-alleviating pad structure.

公开(公告)号：US20160035641A1

公开(公告)日：2016-02-04

申请号：US14875917

申请日：2015-10-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Brian M. Erwin ,  Karen P. McLaughlin ,  Ekta Misra

IPC: H01L23/31 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L23/3171 ,  H01L21/76804 ,  H01L21/7681 ,  H01L21/76816 ,  H01L23/3192 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/1031 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05094 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device includes forming a passivation layer on a least one capping layer of the semiconductor device, and forming an encapsulant layer on the passivation layer. The method further includes patterning the encapsulant layer to expose a portion of the passivation layer and forming a final via opening in the passivation layer. A conductive material is deposited in the final via opening. The method further includes planarizing the conductive material until reaching a remaining portion of the encapsulant layer such that the conductive material is flush with the encapsulant layer and the passivation layer is preserved.

Abstract translation: 制造半导体器件的方法包括在半导体器件的至少一个覆盖层上形成钝化层，并在钝化层上形成密封剂层。 该方法还包括图案化封装层以暴露钝化层的一部分并在钝化层中形成最终的通孔。 导电材料沉积在最终通孔中。 该方法还包括平坦化导电材料，直到到达封装层的剩余部分，使得导电材料与密封剂层齐平并且保护钝化层。

公开(公告)号：US09842810B1

公开(公告)日：2017-12-12

申请号：US15176595

申请日：2016-06-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ekta Misra ,  Mukta G. Farooq ,  Krishna Tunga

IPC: H01L23/00 ,  H01L21/3205 ,  H01L23/528 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/32051 ,  H01L23/3171 ,  H01L23/5283

Abstract: Structure and method for reducing thermal-mechanical stresses generated for a semiconductor device are provided, which includes a tiled-stress-alleviating pad structure.