公开(公告)号：US10049897B2

公开(公告)日：2018-08-14

申请号：US15421737

申请日：2017-02-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L21/306 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, an interconnect structure can include: a photosensitive polyimide (PSPI) layer including a pedestal portion; a controlled collapse chip connection (C4) bump overlying the pedestal portion of the PSPI layer; a solder overlying the C4 bump and contacting a side of the C4 bump; and an underfill layer abutting the pedestal portion of the PSPI and the C4 bump, wherein the underfill layer and the solder form a first interface separated from the PSPI pedestal.

公开(公告)号：US20170312841A1

公开(公告)日：2017-11-02

申请号：US15654130

申请日：2017-07-19

Applicant: GlobalFoundries Inc.

Inventor： Stephen P. Ayotte ,  Glen E. Richard ,  Timothy D. Sullivan ,  Timothy M. Sullivan

IPC: B23K1/002 ,  B23K1/00 ,  H05K3/34

CPC classification number: B23K1/002 ,  B23K1/0016 ,  H05K3/3436 ,  H05K3/3494 ,  H05K2203/101 ,  Y10T29/49144 ,  Y10T29/53178

Abstract: Methods and apparatus for joining a chip with a substrate. The chip is moved by with a pick-and-place machine from a first location to a second location proximate to the substrate over a first time. In response to moving the chip in a motion path from the first location to the second location, a plurality of solder bumps carried on the chip are liquefied over a second time that is less than the first time. While the solder bumps are liquefied, the chip is placed by the pick-and-place machine onto the substrate.

公开(公告)号：US09776270B2

公开(公告)日：2017-10-03

申请号：US14043047

申请日：2013-10-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen P. Ayotte ,  Glen E. Richard ,  Timothy D. Sullivan ,  Timothy M. Sullivan

IPC: H05K3/34 ,  B23K1/002 ,  B23K1/00

CPC classification number: B23K1/002 ,  B23K1/0016 ,  H05K3/3436 ,  H05K3/3494 ,  H05K2203/101 ,  Y10T29/49144 ,  Y10T29/53178

Abstract: Methods and apparatus for joining a chip with a substrate. The chip is moved by with a pick-and-place machine from a first location to a second location proximate to the substrate over a first time. In response to moving the chip in a motion path from the first location to the second location, a plurality of solder bumps carried on the chip are liquefied over a second time that is less than the first time. While the solder bumps are liquefied, the chip is placed by the pick-and-place machine onto the substrate.

公开(公告)号：US09484301B2

公开(公告)日：2016-11-01

申请号：US14718466

申请日：2015-05-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Max G. Levy ,  Gary L. Milo ,  Matthew D. Moon ,  Anthony C. Speranza ,  Timothy D. Sullivan ,  David C. Thomas ,  Steven S. Williams

IPC: H01L23/528 ,  H01L21/768 ,  H01L49/02 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76883 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer.

公开(公告)号：US09331037B2

公开(公告)日：2016-05-03

申请号：US14886177

申请日：2015-10-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L21/44 ,  H01L21/4763 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/03845 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/11011 ,  H01L2224/1134 ,  H01L2224/11472 ,  H01L2224/11616 ,  H01L2224/1162 ,  H01L2224/1182 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/2064

Abstract: “Thick line dies” that, during manufacture, avoid locating an upstanding edge of a photoresist layer (for example, the edge of a dry film photoresist layer) on top of a “discontinuity.” In this way solder does not flow into the mechanical interface between the photoresist layer and the layer under the photoresist layer in the vicinity of an upstanding edge of the photoresist layer.

Abstract translation: “粗线模具”，在制造过程中，避免在“不连续”的顶部定位光致抗蚀剂层（例如，干膜光致抗蚀剂层的边缘）的直立边缘。这样焊料不会流入机械 光致抗蚀剂层和光致抗蚀剂层下面的层之间在光致抗蚀剂层的直立边缘附近的界面。

公开(公告)号：US10245667B2

公开(公告)日：2019-04-02

申请号：US15654130

申请日：2017-07-19

Applicant: GlobalFoundries Inc.

Inventor： Stephen P. Ayotte ,  Glen E. Richard ,  Timothy D. Sullivan ,  Timothy M. Sullivan

IPC: H05K13/04 ,  B23K1/002 ,  B23K1/00 ,  H05K3/34

Abstract: Methods and apparatus for joining a chip with a substrate. The chip is moved by with a pick-and-place machine from a first location to a second location proximate to the substrate over a first time. In response to moving the chip in a motion path from the first location to the second location, a plurality of solder bumps carried on the chip are liquefied over a second time that is less than the first time. While the solder bumps are liquefied, the chip is placed by the pick-and-place machine onto the substrate.

公开(公告)号：US09508578B2

公开(公告)日：2016-11-29

申请号：US14171874

申请日：2014-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shawn A. Adderly ,  Samantha D. DiStefano ,  Jeffrey P. Gambino ,  Max G. Levy ,  Max L. Lifson ,  Jed H. Rankin ,  Timothy D. Sullivan

IPC: H01L21/67 ,  H01L21/00 ,  G01F1/76

CPC classification number: H01L21/67288 ,  G01F1/76 ,  H01L21/00 ,  H01L21/67109

Abstract: An apparatus and method for leak detection of coolant gas from a chuck. The apparatus includes a chuck having a top surface and configured to clamp a substrate to the top surface, the chuck having one or more recessed regions in the top surface, the recessed regions configured to allow a cooling gas to contact a backside of the substrate; a cooling gas inlet and a cooling gas outlet connected to the one or more recessed regions; a first measurement device connected to the cooling gas inlet and configured to measure a first amount of cooling gas entering the cooling gas inlet and a second measurement device connected to the cooling gas outlet and configured to measure a second amount of cooling gas exiting from the cooling gas outlet; and a controller configured to determine a difference between the first amount of cooling gas and the second amount of cooling gas.

Abstract translation: 一种用于从卡盘泄漏检测冷却剂气体的装置和方法。 该装置包括具有顶表面并被配置为将基板夹持到顶表面的卡盘，卡盘在顶表面中具有一个或多个凹陷区域，凹陷区域被配置为允许冷却气体接触基板的背面; 连接到所述一个或多个凹陷区域的冷却气体入口和冷却气体出口; 连接到冷却气体入口并被配置成测量进入冷却气体入口的第一量的冷却气体的第一测量装置和连接到冷却气体出口的第二测量装置，其被配置成测量从冷却出口排出的第二量的冷却气体 气体出口; 以及控制器，被配置为确定所述第一冷却气体量与所述第二冷却气体量之间的差。

公开(公告)号：US20160043048A1

公开(公告)日：2016-02-11

申请号：US14886177

申请日：2015-10-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/03845 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/11011 ,  H01L2224/1134 ,  H01L2224/11472 ,  H01L2224/11616 ,  H01L2224/1162 ,  H01L2224/1182 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/2064

Abstract: “Thick line dies” that, during manufacture, avoid locating an upstanding edge of a photoresist layer (for example, the edge of a dry film photoresist layer) on top of a “discontinuity.” In this way solder does not flow into the mechanical interface between the photoresist layer and the layer under the photoresist layer in the vicinity of an upstanding edge of the photoresist layer.

公开(公告)号：US09472490B1

公开(公告)日：2016-10-18

申请号：US14824409

申请日：2015-08-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Timothy M. Sullivan ,  Glen E. Richard ,  Stephen P. Ayotte ,  Timothy D. Sullivan

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05017 ,  H01L2224/05026 ,  H01L2224/05547 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/05576 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/14104 ,  H01L2224/16225 ,  H01L2924/01083 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/014

Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure with a recessed solder bump area, and methods of forming the same. An IC structure according to embodiments of the present disclosure can include: a semiconductor material, wherein an upper surface of the semiconductor material includes a non-recessed area and a recessed area laterally separated from each other, the recessed area of the upper surface being shaped to receive a solder bump therein; at least one first through-semiconductor via (TSV) positioned within the semiconductor material and including an upper surface protruding from the recessed area of the semiconductor material; and a metal layer formed over the recessed area and electrically connected to the at least one first TSV.

Abstract translation: 本公开的实施例提供具有凹陷焊料凸块区域的集成电路（IC）结构及其形成方法。 根据本公开实施例的IC结构可以包括：半导体材料，其中半导体材料的上表面包括彼此横向分离的非凹陷区域和凹陷区域，上表面的凹陷区域成形 在其中接收焊料凸块; 至少一个位于所述半导体材料内的第一贯穿半导体通孔（TSV），并且包括从所述半导体材料的凹陷区域突出的上表面; 以及形成在所述凹陷区域上并电连接到所述至少一个第一TSV的金属层。

公开(公告)号：US09318414B2

公开(公告)日：2016-04-19

申请号：US14065454

申请日：2013-10-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Fen Chen ,  Minhua Lu ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/48 ,  H01L23/522

CPC classification number: H01L23/481 ,  H01L23/5226 ,  H01L2224/11 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure generally provides for integrated circuit (IC) structures with through-semiconductor vias (TSV). In an embodiment, an IC structure may include a through-semiconductor via (TSV) embedded in a substrate, the TSV having a cap; a dielectric layer adjacent to the substrate; a metal layer adjacent to the dielectric layer; a plurality of vias each embedded within the dielectric layer and coupling the metal layer to the cap of the TSV at respective contact points, wherein the plurality of vias is configured to create a substantially uniform current density throughout the TSV.

Abstract translation: 本公开通常提供具有贯穿半导体通孔（TSV）的集成电路（IC）结构。 在一个实施例中，IC结构可以包括嵌入在衬底中的贯穿半导体通孔（TSV），TSV具有帽; 与基板相邻的电介质层; 与介电层相邻的金属层; 多个通孔，每个通孔嵌入在电介质层内，并将金属层耦合到各个接触点处的TSV的盖，其中多个通孔被配置成在整个TSV中产生基本均匀的电流密度。