公开(公告)号：US20190096679A1

公开(公告)日：2019-03-28

申请号：US15712996

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Balaji Kannan ,  Bala Haran ,  Vimal K. Kamineni ,  Sungkee Han ,  Neal Makela ,  Suraj K. Patil ,  Pei Liu ,  Chih-Chiang Chang ,  Katsunori Onishi ,  Keith Kwong Hon Wong ,  Ruilong Xie ,  Chanro Park ,  Min Gyu Sung

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods for forming a structure for a field-effect transistor. A gate cavity is formed in a dielectric layer that includes a bottom surface and a plurality sidewalls that extend to the bottom surface. A gate dielectric layer is formed at the sidewalls and the bottom surface of the gate cavity. A work function metal layer is deposited on the gate dielectric layer at the sidewalls and the bottom surface of the gate cavity. A fill metal layer is deposited inside the gate cavity after the work function metal layer is deposited. The fill metal layer is formed in direct contact with the work function metal layer.

公开(公告)号：US10157796B1

公开(公告)日：2018-12-18

申请号：US15811953

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Laertis Economikos ,  Chanro Park ,  Ruilong Xie ,  Pei Liu

IPC: H01L21/8234 ,  H01L31/05 ,  H01L21/311 ,  H01L23/544 ,  H01L21/027 ,  H01L21/3105 ,  H01L29/66 ,  H01L21/02

Abstract: The disclosure relates to methods including: forming a soft mask; forming a first marking trench within a portion of the soft mask by selectively removing a portion of the soft mask at a first location, over one of a pair of gate trenches; forming an insulative liner on the soft mask and within the first marking trench; forming an anti-reflective film on the insulative liner and within the first marking trench; selectively removing the anti-reflective film and the insulative liner at a second location to expose a portion of the soft mask positioned over the other one of the pair of gate trenches; forming a second marking trench by removing another portion of the soft mask at the second location; and removing a portion of the soft mask at the first and second marking trenches to expose a lower surface of each of the pair of gate trenches.

公开(公告)号：US10056303B1

公开(公告)日：2018-08-21

申请号：US15494119

申请日：2017-04-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj Kumar Patil ,  Katsunori Onishi ,  Pei Liu ,  Chih-Chiang Chang

IPC: H01L21/82 ,  H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/4966

Abstract: A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.