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公开(公告)号:US10930549B2
公开(公告)日:2021-02-23
申请号:US16573209
申请日:2019-09-17
Applicant: GLOBALFOUNDRIES INC.
Inventor: Jinsheng Gao , Daniel Jaeger , Chih-Chiang Chang , Michael Aquilino , Patrick Carpenter , Junsic Hong , Mitchell Rutkowski , Haigou Huang , Huy Cao
IPC: H01L29/66 , H01L29/78 , H01L21/768 , H01L21/28 , H01L21/311 , H01L29/417
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.
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2.
公开(公告)号:US10714376B2
公开(公告)日:2020-07-14
申请号:US16016910
申请日:2018-06-25
Applicant: GLOBALFOUNDRIES INC.
Inventor: Chih-Chiang Chang , Haifeng Sheng , Jiehui Shu , Haigou Huang , Pei Liu , Jinping Liu , Haiting Wang , Daniel J. Jaeger
IPC: H01L29/66 , H01L29/78 , H01L21/762 , H01L27/088 , H01L21/8234 , H01L21/768
Abstract: The present disclosure relates to methods for forming fill materials in trenches having different widths and related structures. A method may include: forming a first fill material in a first and second trench where the second trench has a greater width than the first trench; removing a portion of the first fill material from each trench and forming a second fill material over the first fill material; removing a portion of the first and second fill material within the second trench; and forming a third fill material in the second trench. The structure may include a first fill material in trenches having different widths wherein the upper surfaces of the first fill material in each trench are substantially co-planar. The structure may also include a second fill material on the first fill material in each trench, the second fill material having a substantially equal thickness in each trench.
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公开(公告)号:US10431500B1
公开(公告)日:2019-10-01
申请号:US15936734
申请日:2018-03-27
Applicant: GLOBALFOUNDRIES INC.
Inventor: Asli Sirman , Jiehui Shu , Chih-Chiang Chang , Huy Cao , Haigou Huang , Jinping Liu
IPC: H01L21/00 , H01L21/8234 , H01L29/66 , H01L21/762 , H01L27/088 , H01L29/78
Abstract: Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.
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公开(公告)号:US10008385B1
公开(公告)日:2018-06-26
申请号:US15612335
申请日:2017-06-02
Applicant: GLOBALFOUNDRIES Inc.
Inventor: Ashish Kumar Jha , Haiting Wang , Chih-Chiang Chang , Mitchell Rutkowski
IPC: H01L21/28 , H01L21/768
CPC classification number: H01L21/28132 , H01L21/76834 , H01L21/76897
Abstract: Methods of forming a sacrificial gate cap and a self-aligned contact for a device structure. A gate electrode is arranged between a first sidewall spacer and a second sidewall spacer. A top surface of the gate electrode is recessed to open a space above the top surface of the recessed gate electrode that partially exposes the first and second sidewall spacers. Respective sections of the first and second sidewall spacers, which are arranged above the top surface of the recessed gate electrode, are removed in order to increase a width of the space. A sacrificial cap is formed in the widened space.
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公开(公告)号:US20190326416A1
公开(公告)日:2019-10-24
申请号:US15956306
申请日:2018-04-18
Applicant: GLOBALFOUNDRIES Inc.
Inventor: Haigou Huang , Jiehui Shu , Chih-Chiang Chang , Xingzhao Shi , Jinsheng Gao , Huy Cao
Abstract: Structures for a field-effect transistor and methods of forming a structure for field-effect transistor. A gate electrode is arranged in a lower portion of a trench in an interlayer dielectric layer, and a liner is formed inside an upper portion of the trench and over a top surface of the interlayer dielectric layer. A dielectric material is deposited in in the upper portion of the trench and over the liner on the top surface of the interlayer dielectric layer. The dielectric material is polished with a polishing process to remove the dielectric material from the liner on the top surface of the interlayer dielectric layer and to form a cap comprised of the dielectric material in the upper portion of the trench. The liner on the interlayer dielectric layer operates as a polish stop during the polishing process.
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公开(公告)号:US10211103B1
公开(公告)日:2019-02-19
申请号:US15787257
申请日:2017-10-18
Applicant: GLOBALFOUNDRIES Inc.
Inventor: Haigou Huang , Dinesh Koli , Yuan Zhou , Xingzhao Shi , Chih-Chiang Chang , Tai Fong Chao
IPC: H01L21/28 , H01L21/768 , H01L29/66 , H01L23/522 , H01L23/532
Abstract: Methods of forming a SAC cap with SiN U-shaped and oxide T-shaped structures and the resulting devices are provided. Embodiments include forming a substrate with a trench and a plurality of gate structures; forming a nitride liner over portions of the substrate and along sidewalls of each gate structure; forming an ILD between each gate structure and in the trench; recessing each gate structure between the ILD; forming a U-shaped nitride liner over each recessed gate structure; forming an a-Si layer over the nitride liner and the U-shaped nitride liner; removing portions of the nitride liner, the U-shaped nitride liner and the a-Si layer; forming a W layer over portions of the substrate adjacent to and between the a-Si layer; forming an oxide liner over the nitride liner, the U-shaped nitride liner and along sidewalls of the W layer; and forming an oxide layer over portions of the oxide liner.
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公开(公告)号:US10014180B1
公开(公告)日:2018-07-03
申请号:US15681654
申请日:2017-08-21
Applicant: GLOBALFOUNDRIES Inc.
Inventor: Neal A. Makela , Vimal K. Kamineni , Pei Liu , Chih-Chiang Chang
IPC: H01L21/285 , H01L21/02 , H01L21/3105 , H01L29/423
CPC classification number: H01L21/28568 , H01L21/0217 , H01L21/28079 , H01L21/28088 , H01L21/28556 , H01L21/31055 , H01L29/42364 , H01L29/42376 , H01L29/4238 , H01L29/4966 , H01L29/66545 , H01L29/66568 , H01L2029/42388
Abstract: A structure and method for forming a tungsten region for a replacement metal gate (RMG). The method for forming the tungsten region may include, among other things, forming a first tungsten region i.e., tungsten seed layer, on a liner in a trench of a dielectric layer; removing a portion of the liner and the tungsten seed layer to expose an uppermost surface of a work function metal (WFM) layer wherein an uppermost surface of the liner and tungsten seed layer is positioned below an uppermost surface of the dielectric layer; and forming a second tungsten region from the tungsten seed layer. The tungsten region may be formed to contact the uppermost surface liner, the uppermost surface of WFM layer, and/or the sidewalls of the trench. The tungsten region may include a single crystallographic orientation. The tungsten region may also include an uppermost surface with a substantially arcuate cross-sectional geometry.
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公开(公告)号:US10460986B2
公开(公告)日:2019-10-29
申请号:US15882291
申请日:2018-01-29
Applicant: GLOBALFOUNDRIES INC.
Inventor: Jinsheng Gao , Daniel Jaeger , Chih-Chiang Chang , Michael Aquilino , Patrick Carpenter , Junsic Hong , Mitchell Rutkowski , Haigou Huang , Huy Cao
IPC: H01L29/66 , H01L21/768 , H01L21/28 , H01L21/311 , H01L29/417
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.
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9.
公开(公告)号:US20190393077A1
公开(公告)日:2019-12-26
申请号:US16016910
申请日:2018-06-25
Applicant: GLOBALFOUNDRIES INC.
Inventor: Chih-Chiang Chang , Haifeng` Sheng , Jiehui Shu , Haigou Huang , Pei Liu , Jinping Liu , Haiting Wang , Daniel J. Jaeger
IPC: H01L21/762 , H01L29/66 , H01L21/768 , H01L29/78 , H01L21/8234 , H01L27/088
Abstract: The present disclosure relates to methods for forming fill materials in trenches having different widths and related structures. A method may include: forming a first fill material in a first and second trench where the second trench has a greater width than the first trench; removing a portion of the first fill material from each trench and forming a second fill material over the first fill material; removing a portion of the first and second fill material within the second trench; and forming a third fill material in the second trench. The structure may include a first fill material in trenches having different widths wherein the upper surfaces of the first fill material in each trench are substantially co-planar. The structure may also include a second fill material on the first fill material in each trench, the second fill material having a substantially equal thickness in each trench.
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公开(公告)号:US20190355624A1
公开(公告)日:2019-11-21
申请号:US16529162
申请日:2019-08-01
Applicant: GLOBALFOUNDRIES INC.
Inventor: Asli Sirman , Jiehui Shu , Chih-Chiang Chang , Huy Cao , Haigou Huang , Jinping Liu
IPC: H01L21/8234 , H01L21/762 , H01L27/088 , H01L29/66
Abstract: Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.
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