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    Contact structures
    2.
    发明授权
    Contact structures 有权

    公开(公告)号：US10510613B2

    公开(公告)日：2019-12-17

    申请号：US15878081

    申请日：2018-01-23

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jiehui Shu ,  Xusheng Wu ,  Haigou Huang ,  John H. Zhang ,  Pei Liu ,  Laertis Economikos

    IPC: H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L23/535 ,  H01L21/28

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a contact over an active gate structure and methods of manufacture. The structure includes: an active gate structure composed of conductive material located between sidewall material; an upper sidewall material above the sidewall material, the upper sidewall material being different material than the sidewall material; and a contact structure in electrical contact with the conductive material of the active gate structure. The contact structure is located between the sidewall material and between the upper sidewall material.

    CONTACT STRUCTURES
    3.
    发明申请
    CONTACT STRUCTURES 审中-公开

    公开(公告)号：US20190229019A1

    公开(公告)日：2019-07-25

    申请号：US15878081

    申请日：2018-01-23

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jiehui Shu ,  Xusheng Wu ,  Haigou Huang ,  John H. Zhang ,  Pei Liu ,  Laertis Economikos

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L23/535 ,  H01L21/768

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a contact over an active gate structure and methods of manufacture. The structure includes: an active gate structure composed of conductive material located between sidewall material; an upper sidewall material above the sidewall material, the upper sidewall material being different material than the sidewall material; and a contact structure in electrical contact with the conductive material of the active gate structure. The contact structure is located between the sidewall material and between the upper sidewall material.

    Active gate contacts and method of fabrication thereof
    4.
    发明授权
    Active gate contacts and method of fabrication thereof 有权

    公开(公告)号：US10347541B1

    公开(公告)日：2019-07-09

    申请号：US15962808

    申请日：2018-04-25

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jiehui Shu ,  David Paul Brunco ,  Pei Liu ,  Shariq Siddiqui ,  Jinping Liu

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08

    Abstract: A method of forming contacts over active gates is provided. Embodiments include forming first and second gate structures over a portion of a fin; forming a first and second RSD in a portion of the fin between the first gate structures and between the first and the second gate structure, respectively; forming TS structures over the first and second RSD; forming a first cap layer over the first and second gate structures or over the TS structures; forming a metal oxide liner over the substrate, trenches formed; filling the trenches with a second cap layer; forming an ILD layer over the substrate; forming a CA through a first portion of the ILD and metal oxide layer down to the TS structures over the second RSD; and forming a CB through a second portion of the ILD and metal oxide layer down to the first gate structures.

    Methods of forming field effect transistors (FETS) with gate cut isolation regions between replacement metal gates
    5.
    发明授权
    Methods of forming field effect transistors (FETS) with gate cut isolation regions between replacement metal gates 有权

    公开(公告)号：US10090402B1

    公开(公告)日：2018-10-02

    申请号：US15658835

    申请日：2017-07-25

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Chanro Park ,  Chang Ho Maeng ,  Pei Liu ,  Junsic Hong ,  Laertis Economikos ,  Ruilong Xie

    IPC: H01L29/66 ,  H01L29/06

    Abstract: The method includes steps for improving gate cut isolation region critical dimension (CD) control. Prior to replacement metal gate (RMG) formation, a first sacrificial gate adjacent to first and second channel regions and made of a first sacrificial material (e.g., polysilicon or amorphous silicon) is replaced with a second sacrificial gate made of a second sacrificial material (e.g., amorphous carbon) that is more selectively and anisotropically etchable. A cut is made, dividing the second sacrificial gate into first and second sections, and the cut is then filled with a dielectric to form the gate cut isolation region. The second sacrificial material ensures that, when an opening in a mask pattern used to form the cut extends over a gate sidewall spacer and interlayer dielectric (ILD) material, recesses are not form within the spacer or ILD. Thus, the CD of the isolation region can be controlled.

    Integration scheme for gate height control and void free RMG fill
    9.
    发明授权
    Integration scheme for gate height control and void free RMG fill 有权

    公开(公告)号：US10354928B2

    公开(公告)日：2019-07-16

    申请号：US16038977

    申请日：2018-07-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Suraj Kumar Patil ,  Katsunori Onishi ,  Pei Liu ,  Chih-Chiang Chang

    IPC: H01L21/82 ,  H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/49

    Abstract: A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.

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