公开(公告)号：US09805990B2

公开(公告)日：2017-10-31

申请号：US14751557

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andres Bryant ,  Edward J. Nowak ,  Robert R. Robison

IPC: H01L21/84 ,  G05F3/16 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L21/845 ,  G05F3/16 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/78696

Abstract: An integrated circuit having a reference device and method of forming the same. A reference device is disclosed having: a fully depleted n-type MOSFET implemented as a long channel device having a substantially undoped body; and a fully depleted p-type MOSFET implemented with as a long channel device having a substantially undoped body; wherein the n-type MOSFET and p-type MOSFET are connected in series and employ identical gate stacks, wherein each has a gate electrically coupled to a respective drain to form two diodes, and wherein both diodes are in one of an on state and an off state according to a value of an electrical potential applied across the n-type MOSFET and p-type MOSFET.

公开(公告)号：US09349749B2

公开(公告)日：2016-05-24

申请号：US14832166

申请日：2015-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Viorel Ontalus ,  Robert R. Robison ,  Xin Wang

IPC: H01L21/331 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/1203 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78621

Abstract: A semiconductor device comprises first and second gate stacks formed on a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a dielectric layer interposed between a bulk substrate layer and an active semiconductor layer. A first extension implant portion is disposed adjacent to the first gate stack and a second extension implant portion is disposed adjacent to the second gate stack. A halo implant extends continuously about the trench. A butting implant extends between the trench and the dielectric layer. An epitaxial layer is formed at the exposed region such that the butting implant is interposed between the epitaxial layer and the dielectric layer.

Abstract translation: 半导体器件包括形成在绝缘体上半导体（SOI）衬底上的第一和第二栅极叠层。 SOI衬底包括介于主衬底层和有源半导体层之间的电介质层。 第一延伸植入部分邻近第一栅极堆叠设置，并且第二延伸注入部分邻近第二栅极堆叠设置。 晕轮植入物围绕沟槽连续延伸。 对接植入物在沟槽和电介质层之间延伸。 在暴露区域形成外延层，使得对接植入物介于外延层和电介质层之间。

公开(公告)号：US09972550B2

公开(公告)日：2018-05-15

申请号：US14873677

申请日：2015-10-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Edward J. Nowak ,  Robert R. Robison ,  Lyndon R. Logan

IPC: H01L31/062 ,  H01L29/66 ,  G06F17/50 ,  H01L21/66 ,  H01L27/088 ,  G01B7/00

CPC classification number: H01L22/34 ,  G01B7/00 ,  G01B7/02 ,  H01L21/823425 ,  H01L21/823431 ,  H01L22/32 ,  H01L27/0886

Abstract: A source/drain epitaxial electrical monitor and methods of characterizing epitaxial growth through capacitance measurements are provided. The structure includes a plurality of fin structures; one or more gate structures, perpendicular to and intersecting the plurality of fin structures. The structure further includes a first connection by a first contact at one fin-end of every other fin structure of the plurality of fin structures, and a second connection by a second contact at one end of an alternate fin structure of the plurality of fin structures.

公开(公告)号：US09852956B2

公开(公告)日：2017-12-26

申请号：US14613570

申请日：2015-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lyndon Ronald Logan ,  Edward J. Nowak ,  Robert R. Robison ,  Jonathan K. Winslow

IPC: H01L21/66 ,  H01L21/8234 ,  H01L29/45 ,  G01R31/26

CPC classification number: H01L22/14 ,  G01R31/2621 ,  H01L21/823431 ,  H01L22/34 ,  H01L29/45

Abstract: Various embodiments provide systems, computer program products and computer implemented methods. In some embodiments, a system includes a computer-implemented method of determining a laterally diffuse dopant profile in semiconductor structures by providing first and second semiconductor structures having plurality of gate array structures in a silicided region separated from each other by a first distance and second distance. A potential difference is applied across the plurality of gate array structures and resistances are determined. A linear-regression fit is performed on measured resistance versus the first distance and the second distance with an extrapolated x equals 0 and a y-intercept to determine a laterally diffused dopant-profile under the plurality of gate array structures based on a semiconductor device model.

公开(公告)号：US20160379999A1

公开(公告)日：2016-12-29

申请号：US14748355

申请日：2015-06-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony I. Chou ,  Sungjae Lee ,  Joseph M. Lukaitis ,  Robert R. Robison

IPC: H01L27/12 ,  H01L21/3205 ,  H01L21/22 ,  H01L23/522 ,  H01L23/373

CPC classification number: H01L27/1207 ,  H01L23/3677 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5228 ,  H01L23/535

Abstract: Methods and structures for capacitively isolating a heat shield from a handle wafer of a silicon-on-insulator substrate. A contact plug is located in a trench extending through a trench isolation region in a device layer of the silicon-on-insulator substrate and at least partially through a buried insulator layer of the silicon-on-insulator substrate. The heat shield is located in an interconnect structure, which also includes a wire coupling the heat shield with the contact plug. An isolation structure is positioned between the contact plug and a portion of the handle wafer. The isolation structure provides the capacitive isolation.

Abstract translation: 将隔热层与绝缘体上硅衬底的处理晶片电容性隔离的方法和结构。 接触插塞位于延伸穿过绝缘体上硅衬底的器件层中的沟槽隔离区域并且至少部分地穿过绝缘体上硅衬底的掩埋绝缘体层的沟槽中。 隔热罩位于互连结构中，其还包括将隔热罩与接触插头连接的线。 隔离结构位于接触塞和处理晶片的一部分之间。 隔离结构提供电容隔离。

公开(公告)号：US09530798B1

公开(公告)日：2016-12-27

申请号：US14748355

申请日：2015-06-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony I. Chou ,  Sungjae Lee ,  Joseph M. Lukaitis ,  Robert R. Robison

IPC: H01L23/552 ,  H01L23/66 ,  H01L27/12 ,  H01L23/522 ,  H01L23/373 ,  H01L21/22 ,  H01L21/3205

CPC classification number: H01L27/1207 ,  H01L23/3677 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5228 ,  H01L23/535

Abstract: Methods and structures for capacitively isolating a heat shield from a handle wafer of a silicon-on-insulator substrate. A contact plug is located in a trench extending through a trench isolation region in a device layer of the silicon-on-insulator substrate and at least partially through a buried insulator layer of the silicon-on-insulator substrate. The heat shield is located in an interconnect structure, which also includes a wire coupling the heat shield with the contact plug. An isolation structure is positioned between the contact plug and a portion of the handle wafer. The isolation structure provides the capacitive isolation.

Abstract translation: 将隔热层与绝缘体上硅衬底的处理晶片电容性隔离的方法和结构。 接触插塞位于延伸穿过绝缘体上硅衬底的器件层中的沟槽隔离区域并且至少部分地穿过绝缘体上硅衬底的掩埋绝缘体层的沟槽中。 隔热罩位于互连结构中，其还包括将隔热罩与接触插头连接的线。 隔离结构位于接触塞和处理晶片的一部分之间。 隔离结构提供电容隔离。