公开(公告)号：US20150357434A1

公开(公告)日：2015-12-10

申请号：US14827510

申请日：2015-08-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Linus Jang ,  Sivananda K. Kanakasabapathy ,  Sanjay C. Mehta ,  Soon-Cheon Seo ,  Raghavasimhan Sreenivasan

IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/283

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

公开(公告)号：US20150214331A1

公开(公告)日：2015-07-30

申请号：US14168112

申请日：2014-01-30

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Linus Jang ,  Sivananda K. Kanakasabapathy ,  Sanjay C. Mehta ,  Soon-Cheon Seo ,  Raghavasimhan Sreenivasan

IPC: H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/2018 ,  H01L21/28238 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7855 ,  H01L2029/7858

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

Abstract translation: 制造半导体器件的方法包括在半导体衬底上形成至少一个半导体鳍片。 在布置在散热片上的蚀刻停止层上形成多个栅极形成层。 多个栅极形成层包括由电介质材料形成的虚拟栅极层。 图案化多个栅极形成层以在蚀刻停止层上形成多个虚拟栅极元件。 每个伪栅极元件由电介质材料形成。 蚀刻形成在虚拟栅极元件上的间隔层，以在虚拟栅极元件的每个侧壁上形成间隔物。 位于每个伪栅元件之间的蚀刻停止层的一部分被蚀刻以暴露半导体鳍片的一部分。 半导体材料从半导体鳍片的暴露部分外延生长以形成源极/漏极区域。

公开(公告)号：US10297510B1

公开(公告)日：2019-05-21

申请号：US15962536

申请日：2018-04-25

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Soon-Cheon Seo ,  Fee Li Lie ,  Linus Jang

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/092

Abstract: A method for fabricating a multiple gate width structure for an integrated circuit is described. A fin on a semiconductor substrate with a first hard mask layer is covered by a first and second sacrificial gate each of which includes a second hard mask layer. Spacer layers and a dielectric layer are formed over the first and second sacrificial gate structures. The resulting structure is planarized so that the first and second sacrificial gate structures and the dielectric layer have coplanar top surfaces. The first and second sacrificial gate structures are removed to respectively form first and second trench recesses in the dielectric layer. The trench recesses are filled with a conductor to form permanent gate structures. A first permanent gate structure is formed in the first trench recess has a first length and a second permanent gate structure is formed in the second trench recess has a second length greater than the first length.

公开(公告)号：US09818873B2

公开(公告)日：2017-11-14

申请号：US14879220

申请日：2015-10-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emre Alptekin ,  Lars W. Liebmann ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Ravikumar Ramachandran ,  Soon-Cheon Seo ,  Charan V. V. S. Surisetty ,  Mickey H. Yu

IPC: H01L29/40 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L29/7848 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/66636 ,  H01L29/66795

Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a doped silicon layer over a substrate; forming a plurality of fin structures from the doped silicon layer; forming a plurality of gate structures over the plurality of fin structures, each of the plurality of gate structures separated from a neighboring gate structure by a first pitch; forming a mask over the plurality of gate structures, exposing at least one of the plurality of gate structures; removing the at least one of the plurality of gate structures, wherein two of the remaining gate structures after the removing are separated by a second pitch larger than the first pitch; and forming an epitaxial region over the substrate between the two of the remaining gate structures.