公开(公告)号：US20160099302A1

公开(公告)日：2016-04-07

申请号：US14507927

申请日：2014-10-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert Seidel ,  Torsten Huisinga

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/40 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/7685 ,  H01L28/75

Abstract: A method of manufacturing a semiconductor device comprising a capacitor structure is provided, including the steps of forming a first metallization layer comprising a first dielectric layer and a first conductive layer functioning as a lower electrode for the capacitor structure over a semiconductor substrate, forming a barrier layer functioning as a capacitor insulator for the capacitor structure on the first metallization layer, forming a metal layer on the barrier layer and etching the metal layer to form an upper electrode of the capacitor structure.

Abstract translation: 提供一种制造包括电容器结构的半导体器件的方法，包括以下步骤：在半导体衬底上形成第一金属化层，其包括第一电介质层和用作电容器结构的下电极的第一导电层，形成屏障 层作为第一金属化层上的电容器结构的电容绝缘体，在阻挡层上形成金属层，并蚀刻金属层以形成电容器结构的上部电极。

公开(公告)号：US09305878B2

公开(公告)日：2016-04-05

申请号：US14570617

申请日：2014-12-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Torsten Huisinga ,  Carsten Peters ,  Andreas Ott ,  Axel Preusse

IPC: H01L23/522 ,  H01L23/485 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76814 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a metal contact structure, an electrically conductive capping layer formed on the metal contact structure, and a conductive via electrically connected to the metal contact structure through the electrically conductive capping layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，集成电路包括金属接触结构，形成在金属接触结构上的导电覆盖层，以及通过导电覆盖层电连接到金属接触结构的导电通孔。

公开(公告)号：US09287109B2

公开(公告)日：2016-03-15

申请号：US13798764

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Torsten Huisinga ,  Keith Donegan ,  Robert Seidel

IPC: H01L21/308 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/02079 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144

Abstract: One method disclosed herein includes forming a layer of insulating material above a semiconductor substrate, forming a hard mask layer comprised of a metal-containing material above the layer of insulating material, forming a blanket protection layer on the hard mask layer, forming a masking layer above the protection layer, performing at least one etching process on the masking layer to form a patterned masking layer having an opening that stops on and exposes a portion of the blanket protection layer, confirming that the patterned masking layer is properly positioned relative to at least one underlying structure or layer and, after confirming that the patterned masking layer is properly positioned, performing at least one etching process through the patterned masking layer to pattern at least the blanket protection layer.

Abstract translation: 本文公开的一种方法包括在半导体衬底上形成绝缘材料层，在绝缘材料层之上形成由含金属材料构成的硬掩模层，在硬掩模层上形成覆盖层保护层，形成掩模层 在保护层上方，在掩模层上执行至少一个蚀刻工艺，以形成图案化掩模层，该掩模层具有停止并暴露橡皮布保护层的一部分的开口，证实图案化掩模层相对于至少 一个底层结构或层，并且在确认图案化掩模层被正确定位之后，通过图案化掩模层执行至少一个蚀刻工艺，以至少对覆盖保护层进行图案化。

公开(公告)号：US09257329B2

公开(公告)日：2016-02-09

申请号：US14185398

申请日：2014-02-20

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Oliver Mieth ,  Carsten Peters ,  Torsten Huisinga

IPC: H01L21/3105 ,  H01L21/768

CPC classification number: H01L21/76826 ,  H01L21/3105 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76895

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes densifying an upper-surface portion of an ILD layer of dielectric material that overlies a metallization layer above a semiconductor substrate to form a densified surface layer of dielectric material. The densified surface layer and the ILD layer are etched through to expose a metal line of the metallization layer.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括使覆盖在半导体衬底之上的金属化层上的介电材料的ILD层的上表面部分致密化，以形成电介质材料的致密表面层。 蚀刻致密表面层和ILD层以暴露金属化层的金属线。

公开(公告)号：US20140264758A1

公开(公告)日：2014-09-18

申请号：US13798764

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Torsten Huisinga ,  Keith Donegan ,  Robert Seidel

IPC: H01L21/308

CPC classification number: H01L21/02079 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144

Abstract: One method disclosed herein includes forming a layer of insulating material above a semiconductor substrate, forming a hard mask layer comprised of a metal-containing material above the layer of insulating material, forming a blanket protection layer on the hard mask layer, forming a masking layer above the protection layer, performing at least one etching process on the masking layer to form a patterned masking layer having an opening that stops on and exposes a portion of the blanket protection layer, confirming that the patterned masking layer is properly positioned relative to at least one underlying structure or layer and, after confirming that the patterned masking layer is properly positioned, performing at least one etching process through the patterned masking layer to pattern at least the blanket protection layer.

Abstract translation: 本文公开的一种方法包括在半导体衬底上形成绝缘材料层，在绝缘材料层之上形成由含金属材料构成的硬掩模层，在硬掩模层上形成覆盖层保护层，形成掩模层 在保护层上方，在掩模层上执行至少一个蚀刻工艺，以形成图案化掩模层，该掩模层具有停止并暴露橡皮布保护层的一部分的开口，证实图案化掩模层相对于至少 一个底层结构或层，并且在确认图案化掩模层被正确定位之后，通过图案化掩模层执行至少一个蚀刻工艺，以至少对覆盖保护层进行图案化。