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    ESD protection circuit
    12.
    发明授权
    ESD protection circuit 有权
    ESD保护电路

    公开(公告)号：US08853784B2

    公开(公告)日：2014-10-07

    申请号：US13737964

    申请日：2013-01-10

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Da-Wei Lai ,  Handoko Linewih ,  Ying-Chang Lin

    IPC: H01L23/62 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/78 ,  H01L27/0266 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/7816

    Abstract: A device having a substrate defined with a device region which includes an ESD protection circuit is disclosed. The ESD protection circuit has first and second transistors. A transistor includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, and a second diffusion region in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. The device includes a first device well which encompasses the device region and second device wells which are disposed within the first device well. A well contact is coupled to the second device wells. The well contact surrounds the gates of the transistors and abuts the first diffusion regions of the transistors.

    Abstract translation: 公开了一种具有由包括ESD保护电路的器件区限定的衬底的器件。 ESD保护电路具有第一和第二晶体管。 晶体管包括具有第一和第二侧的栅极，与栅极的第一侧相邻的器件区域中的第一扩散区域以及远离栅极的第二侧移位的器件区域中的第二扩散区域。 第一和第二扩散区域包括第一极性类型的掺杂剂。 该装置包括包围装置区域的第一装置井和设置在第一装置井内的第二装置井。 井接触耦合到第二设备井。 阱接触围绕晶体管的栅极并且邻接晶体管的第一扩散区域。

    ESD protection circuit
    13.
    发明授权
    ESD protection circuit 有权
    ESD保护电路

    公开(公告)号：US08847318B2

    公开(公告)日：2014-09-30

    申请号：US13803091

    申请日：2013-03-14

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Da-Wei Lai ,  Handoko Linewih ,  Ying-Chang Lin

    IPC: H01L23/62 ,  H01L29/66 ,  H01L27/02

    CPC classification number: H01L27/0266 ,  H01L27/027 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7835

    Abstract: A device which includes a substrate defined with a device region with an ESD protection circuit having at least first and second transistors is disclosed. Each of the transistors includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, a second diffusion region in the device region displaced away from the second side of the gate, and a drift isolation region disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. The device also includes a drift well which encompasses the second diffusion region. Edges of the drift well do not extend below the gate and is away from a channel region. A drain well is disposed under the second diffusion region and within the drift well.

    Abstract translation: 公开了一种装置，其包括用至少具有第一和第二晶体管的ESD保护电路的器件区限定的衬底。 每个晶体管包括具有第一和第二侧的栅极，与栅极的第一侧相邻的器件区域中的第一扩散区域，远离栅极的第二侧移位的器件区域中的第二扩散区域，以及 漂移隔离区域设置在栅极和第二扩散区域之间。 第一装置阱包围装置区域，第二装置井设置在第一装置井内。 该装置还包括包围第二扩散区域的漂移阱。 漂移井的边缘不延伸到门下方并远离通道区域。 排水井设置在第二扩散区域下方和漂移井内。

    One-time programmable fuse using thin film resistor layer, and related method
    14.
    发明授权
    One-time programmable fuse using thin film resistor layer, and related method 有权

    公开(公告)号：US12176048B2

    公开(公告)日：2024-12-24

    申请号：US18145341

    申请日：2022-12-22

    Applicant: GlobalFoundries Singapore Pte. Ltd.

    Inventor： Siow Lee Chwa ,  Handoko Linewih ,  Yudi Setiawan ,  Qiying Wong

    IPC: G11C17/16 ,  G11C17/18 ,  H01C7/00 ,  H01L23/525

    Abstract: A one-time programmable (OTP) fuse includes a fuse link including a thin film resistor (TFR) layer between a first insulator layer and a second insulator layer. A first terminal of the OTP fuse includes a first conductive pillar through one of the first and second insulator layers and in contact with the TFR layer; and a second terminal of the OTP fuse includes a second conductive pillar through one of the first and second insulator layers and in contact with the TFR layer. The second conductive pillar and the TFR layer have a lateral contact interface having a same shape as an outer portion of the second conductive pillar. The second conductive pillar does not simply land on the TFR layer, but extends through it. Application of a current to the OTP fuse results in programming via rupture of the lateral contact interface (not electromigration in the fuse link).

    Semiconductor device having a capacitive structure and method of forming the same
    15.
    发明授权
    Semiconductor device having a capacitive structure and method of forming the same 有权

    公开(公告)号：US11437406B2

    公开(公告)日：2022-09-06

    申请号：US16721955

    申请日：2019-12-20

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Phyllis Shi Ya Lim ,  Handoko Linewih ,  Shu Zhong ,  Chor Shu Cheng

    IPC: H01L29/94 ,  H01L27/12 ,  H01L29/40 ,  H01L29/78 ,  H01L27/06 ,  H01L27/08

    Abstract: A semiconductor device may be provided, including a substrate which includes a first semiconductor layer having a well region arranged within the first semiconductor layer, a buried insulator layer arranged over the first semiconductor layer, and a second semiconductor layer arranged over the buried insulator layer. The semiconductor device may include a capacitive structure including: the well region, at least one contact to the well region, at least a portion of the buried insulator layer over the well region, at least a portion of the second semiconductor layer, a source region and a drain region arranged over the second semiconductor layer, a gate dielectric layer arranged over the second semiconductor layer and arranged laterally between the source region and the drain region, and a gate layer arranged over the gate dielectric layer. The well region, the source region, and the drain region may have the same conductivity type.

    INTEGRATED CIRCUIT ELECTROSTATIC DISCHARGE PROTECTION
    16.
    发明申请
    INTEGRATED CIRCUIT ELECTROSTATIC DISCHARGE PROTECTION 审中-公开

    公开(公告)号：US20170302066A1

    公开(公告)日：2017-10-19

    申请号：US15132563

    申请日：2016-04-19

    Applicant: Globalfoundries Singapore Pte. Ltd.

    Inventor： Wei Gao ,  Yi Lu ,  Handoko Linewih

    IPC: H02H3/20 ,  H03K5/08 ,  H01L27/02

    CPC classification number: H03K5/08 ,  H01L27/0285 ,  H02H9/046

    Abstract: Integrated circuits (ICs) include electrostatic discharge protection including a transistor having a drain operably coupled to a first rail of the integrated circuit and a source operatively coupled to a second rail of the integrated circuit. A voltage regulating trigger circuit is operatively coupled to the first rail and to a gate of the transistor to turn on of the transistor responsive to an ESD event affecting the integrated circuit, wherein the voltage regulating trigger circuit limits a potential of the first rail to a first potential and a gate potential of the transistor to a second potential, less than the first potential but sufficient to turn the transistor on to conduct current arising from the ESD event from the first rail to the second rail.

    High-voltage devices integrated on semiconductor-on-insulator substrate
    20.
    发明授权
    High-voltage devices integrated on semiconductor-on-insulator substrate 有权

    公开(公告)号：US11545570B2

    公开(公告)日：2023-01-03

    申请号：US16736818

    申请日：2020-01-08

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Pinghui Li ,  Handoko Linewih ,  Darin Arthur Chan ,  Ruchil Kumar Jain

    IPC: H01L29/78 ,  H01L29/66

    Abstract: The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a semiconductor-on-insulator (SOI) substrate having a semiconductor layer, a bulk substrate and an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region disposed on the bulk substrate, an isolation structure extending through the insulating layer and the semiconductor layer and terminates in the bulk substrate, and a gate structure between the source region and the drain region, the gate structure is disposed on the semiconductor layer.

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