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    FinFET with shorter fin height in drain region than source region and related method
    11.
    发明授权
    FinFET with shorter fin height in drain region than source region and related method 有权

    公开(公告)号：US11211453B1

    公开(公告)日：2021-12-28

    申请号：US16936524

    申请日：2020-07-23

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Man Gu ,  Wenjun Li

    IPC: H01L29/08 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66

    Abstract: A FinFET includes a semiconductor fin, and a source region and a drain region in the same semiconductor fin. The drain region has a first fin height above a trench isolation; and the source region has a second fin height above the trench isolation. The first fin height is less than the second fin height. The FinFET may be used, for example, in a scaled laterally diffused metal-oxide semiconductor (LDMOS) application, and exhibits reduced parasitic capacitance for improved radio frequency (RF) performance. A drain extension region may have the first fin height, and a channel region may have the second fin height. A method of making the FinFET is also disclosed.

    INTEGRATED CIRCUIT STRUCTURE INCLUDING ASYMMETRIC, RECESSED SOURCE AND DRAIN REGION AND METHOD FOR FORMING SAME
    12.
    发明申请
    INTEGRATED CIRCUIT STRUCTURE INCLUDING ASYMMETRIC, RECESSED SOURCE AND DRAIN REGION AND METHOD FOR FORMING SAME 有权

    公开(公告)号：US20210273094A1

    公开(公告)日：2021-09-02

    申请号：US16806319

    申请日：2020-03-02

    Applicant: GLOBALFOUNDRIES U.S. INC.

    Inventor： Man Gu ,  Wenjun Li

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165

    Abstract: Integrated circuit (IC) structures including asymmetric, recessed source and drain regions and methods for forming are provided. In an example, the IC structure includes a substrate, a gate structure over the substrate, first and second spacers contacting respective, opposite sidewalls of the gate structure, and source and drain regions on opposite sides of the gate structure. In one configuration, the source region includes an upper source portion having a first lateral width, and a lower source portion having a second lateral width greater than the first lateral width, and the drain region includes an upper drain portion having a third lateral width, and a lower drain portion having a fourth lateral width that is substantially the same as the third lateral width.

    TRANSISTORS WITH HYBRID SOURCE/DRAIN REGIONS
    17.
    发明申请
    TRANSISTORS WITH HYBRID SOURCE/DRAIN REGIONS 有权

    公开(公告)号：US20220028854A1

    公开(公告)日：2022-01-27

    申请号：US16937821

    申请日：2020-07-24

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Wenjun Li ,  Man Gu

    IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A semiconductor substrate includes a first region, a second region, and a first source/drain region in the first region. A semiconductor fin is located over the second region of the semiconductor substrate. The semiconductor fin extends laterally along a longitudinal axis to connect to the first region of the semiconductor substrate. The structure includes a second source/drain region including an epitaxial semiconductor layer coupled to the first semiconductor fin, and a gate structure that extends over the semiconductor fin. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure.

    NOVEL GATE STRUCTURE FOR AN LDMOS TRANSISTOR DEVICE
    18.
    发明申请
    NOVEL GATE STRUCTURE FOR AN LDMOS TRANSISTOR DEVICE 有权

    公开(公告)号：US20210351293A1

    公开(公告)日：2021-11-11

    申请号：US16870356

    申请日：2020-05-08

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Man Gu ,  Wang Zheng ,  Rong-Ting Liou ,  Haiting Wang ,  Wenjun Li

    IPC: H01L29/78 ,  H01L29/66

    Abstract: A device is disclosed that includes a source region positioned in a first doped well region in a semiconductor substrate and a drain region positioned in a second doped well region in the substrate, wherein there is a well gap between the first doped well region and the second doped well region. The device also includes a gate structure that includes a first gate insulation layer positioned above an upper surface of the substrate, wherein the first gate insulation layer extends from a drain-side sidewall of the gate structure to a location above the well gap, and a second gate insulation layer having a first portion positioned above the upper surface of the substrate and a second portion positioned above the first gate insulation layer.

    Methods of forming source/drain regions of a FinFET device and the resulting structures
    19.
    发明授权
    Methods of forming source/drain regions of a FinFET device and the resulting structures 有权

    公开(公告)号：US10964598B2

    公开(公告)日：2021-03-30

    申请号：US16515638

    申请日：2019-07-18

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Bingwu Liu ,  Tao Chu ,  Man Gu

    IPC: H01L21/8234 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

    Abstract: One illustrative method disclosed herein includes forming at least one fin, forming a first recessed layer of insulating material adjacent the at least one fin and forming epi semiconductor material on the at least one fin. In this example, the method also includes forming a second recessed layer of insulating material above the first recessed layer of insulating material, wherein at least a portion of the epi semiconductor material is positioned above a level of the upper surface of the second recessed layer of insulating material, and forming a source/drain contact structure above the second recessed layer of insulating material, wherein the source/drain contact structure is conductively coupled to the epi semiconductor material.

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