公开(公告)号：US20230268401A1

公开(公告)日：2023-08-24

申请号：US17747476

申请日：2022-05-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hong Yu ,  Jianwei Peng ,  Vibhor Jain

IPC: H01L29/417 ,  H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/41708 ,  H01L29/7371 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/42304 ,  H01L29/66242

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with self-aligned asymmetric spacer and methods of manufacture. The structure includes: a base formed on a semiconductor substrate; an asymmetrical spacer surrounding the base; an emitter on a first side of the base and separated from the base by the asymmetrical spacer; and a collector on a second side of the base and separated from the base by the asymmetrical spacer.

公开(公告)号：US11935928B2

公开(公告)日：2024-03-19

申请号：US17747476

申请日：2022-05-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hong Yu ,  Jianwei Peng ,  Vibhor Jain

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L29/41708 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/7371

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with self-aligned asymmetric spacer and methods of manufacture. The structure includes: a base formed on a semiconductor substrate; an asymmetrical spacer surrounding the base; an emitter on a first side of the base and separated from the base by the asymmetrical spacer; and a collector on a second side of the base and separated from the base by the asymmetrical spacer.

公开(公告)号：US11101364B2

公开(公告)日：2021-08-24

申请号：US16296769

申请日：2019-03-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： George R. Mulfinger ,  Hong Yu ,  Man Gu ,  Jianwei Peng ,  Michael Aquilino

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311

Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A gate structure of the field-effect transistor is arranged over an active region comprised of a semiconductor material. A first sidewall spacer is arranged adjacent to the gate structure. A second sidewall spacer includes a section arranged between the first sidewall spacer and the active region. The first sidewall spacer is composed of a low-k dielectric material.

公开(公告)号：US11810951B2

公开(公告)日：2023-11-07

申请号：US17552386

申请日：2021-12-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jianwei Peng ,  Hong Yu ,  Viorel Ontalus

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/66568 ,  H01L29/7848 ,  H01L29/78618

Abstract: Disclosed are a semiconductor structure and method of forming the structure. The structure includes a field effect transistor (FET) with a channel region between source/drain regions that extend through a semiconductor layer and into an insulator layer, that include a first portion in the insulator layer, and a second portion on the first portion in the semiconductor layer and, optionally, extending above the semiconductor layer. The first portion is relatively wide, includes a shallow section below the second portion, and a deep section adjacent to the channel region and overlayed by the semiconductor layer. The uniquely shaped first portion boosts saturation current to be boosted to allow the height of the second portion to be reduced to minimize overlap capacitance. Optionally, each source/drain region includes multiple semiconductor materials including a stress-inducing semiconductor material grown laterally from the semiconductor layer to improve charge carrier mobility in the channel region.

公开(公告)号：US11798948B2

公开(公告)日：2023-10-24

申请号：US17496296

申请日：2021-10-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Kaustubh Shanbhag ,  Eric S. Kozarsky ,  George R. Mulfinger ,  Jianwei Peng

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L29/808

CPC classification number: H01L27/1203 ,  H01L21/7624 ,  H01L21/84 ,  H01L29/808

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor devices with a shared common backside well and methods of manufacture. The structure includes: adjacent gate structures over a semiconductor substrate; a common well in the semiconductor substrate under the adjacent gate structures; a deep trench isolation structure extending through the common well between the adjacent gate structures; and a shared diffusion region between the adjacent gate structures.

公开(公告)号：US20230197783A1

公开(公告)日：2023-06-22

申请号：US17552386

申请日：2021-12-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jianwei Peng ,  Hong Yu ,  Viorel Ontalus

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L29/7848 ,  H01L29/66568 ,  H01L29/0653

Abstract: Disclosed are a semiconductor structure and method of forming the structure. The structure includes a field effect transistor (FET) with a channel region between source/drain regions that extend through a semiconductor layer and into an insulator layer, that include a first portion in the insulator layer, and a second portion on the first portion in the semiconductor layer and, optionally, extending above the semiconductor layer. The first portion is relatively wide, includes a shallow section below the second portion, and a deep section adjacent to the channel region and overlayed by the semiconductor layer. The uniquely shaped first portion boosts saturation current to be boosted to allow the height of the second portion to be reduced to minimize overlap capacitance. Optionally, each source/drain region includes multiple semiconductor materials including a stress-inducing semiconductor material grown laterally from the semiconductor layer to improve charge carrier mobility in the channel region.

公开(公告)号：US20250029869A1

公开(公告)日：2025-01-23

申请号：US18353995

申请日：2023-07-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jianwei Peng ,  Hong Yu

IPC: H01L21/762 ,  H01L21/768

Abstract: An isolation structure for a substrate is disclosed. The isolation structure includes a lower portion having a first liner, and an upper portion having a second liner vertically over the first liner. A first dielectric material is surrounded by the second liner from above and by the first liner from below and laterally. The second liner may include a second dielectric material in at least part thereof. The second liner prevents exposure of end surfaces of a semiconductor layer of the substrate during subsequent processing, which prevents damage such as thinning, agglomeration and/or oxidation that can negatively affect performance of a transistor formed using the semiconductor layer. The second liner also reduces an overall step height of the isolation structure.

公开(公告)号：US12020937B2

公开(公告)日：2024-06-25

申请号：US17701759

申请日：2022-03-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jianwei Peng ,  Hong Yu ,  Man Gu ,  Eric S. Kozarsky

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3215 ,  H01L21/84 ,  H01L27/12 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L21/28052 ,  H01L21/28518 ,  H01L21/32155 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/45 ,  H01L29/4933

Abstract: Semiconductor structures include a channel region, a gate dielectric on the channel region, source and drain structures on opposite sides of the channel region, and a gate conductor between the source and drain structures on the gate dielectric. The source and drain structures include source and drain silicides. The gate conductor includes a gate conductor silicide. The gate conductor silicide is thicker than the source and drain silicides.

公开(公告)号：US20240194535A1

公开(公告)日：2024-06-13

申请号：US18080017

申请日：2022-12-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Navneet Jain ,  Hongru Ren ,  Alexander Derrickson ,  Jianwei Peng ,  Bipul C. Paul

IPC: H01L21/8234 ,  H01L21/768 ,  H01L29/423 ,  H01L29/49 ,  H10B63/00

CPC classification number: H01L21/823475 ,  H01L21/76895 ,  H01L29/42316 ,  H01L29/4933 ,  H10B63/34

Abstract: Structures that include field-effect transistors and methods of forming such structures. The structure comprises a substrate, a dielectric layer on the substrate, a first field-effect transistor including a first semiconductor layer over the dielectric layer and a first gate electrode, and a second field-effect transistor including a second semiconductor layer over the dielectric layer and a second gate electrode adjacent to the first gate electrode. The second semiconductor layer is connected to the first semiconductor layer, and the first and second semiconductor layers are positioned between the first gate electrode and the second gate electrode.

公开(公告)号：US20230307238A1

公开(公告)日：2023-09-28

申请号：US17701759

申请日：2022-03-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jianwei Peng ,  Hong Yu ,  Man Gu ,  Eric S. Kozarsky

IPC: H01L21/28 ,  H01L27/12 ,  H01L29/45 ,  H01L29/49 ,  H01L21/285 ,  H01L21/3215 ,  H01L21/84

CPC classification number: H01L21/28052 ,  H01L27/1203 ,  H01L29/45 ,  H01L29/4933 ,  H01L21/28518 ,  H01L21/32155 ,  H01L21/84

Abstract: Semiconductor structures include a channel region, a gate dielectric on the channel region, source and drain structures on opposite sides of the channel region, and a gate conductor between the source and drain structures on the gate dielectric. The source and drain structures include source and drain silicides. The gate conductor includes a gate conductor silicide. The gate conductor silicide is thicker than the source and drain silicides.