公开(公告)号：US11749747B2

公开(公告)日：2023-09-05

申请号：US17574661

申请日：2022-01-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Judson R. Holt ,  Vibhor Jain ,  Jeffrey B. Johnson ,  John J. Pekarik

IPC: H01L29/737 ,  H01L29/66 ,  H01L21/763 ,  H01L29/06

CPC classification number: H01L29/7371 ,  H01L21/763 ,  H01L29/0642 ,  H01L29/66242

Abstract: Embodiments of the disclosure provide a bipolar transistor structure with a collector on a polycrystalline isolation layer. A polycrystalline isolation layer may be on a substrate, and a collector layer may be on the polycrystalline isolation layer. The collector layer has a first doping type and includes a polycrystalline semiconductor. A base layer is on the collector layer and has a second doping type opposite the first doping type. An emitter layer is on the base layer and has the first doping type. A material composition of the doped collector region is different from a material composition of the base layer.

公开(公告)号：US11710771B2

公开(公告)日：2023-07-25

申请号：US17524043

申请日：2021-11-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alexander Derrickson ,  Judson R. Holt ,  Haiting Wang ,  Jagar Singh ,  Vibhor Jain

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/735 ,  H01L29/737

CPC classification number: H01L29/1008 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/6656 ,  H01L29/66242 ,  H01L29/66553 ,  H01L29/735 ,  H01L29/737

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes an emitter having a raised portion, a collector having a raised portion, and a base having a base layer and an extrinsic base layer stacked with the base layer. The base layer and the extrinsic base layer are positioned in a lateral direction between the raised portion of the emitter and the raised portion of the collector, the base layer has a first width in the lateral direction, the extrinsic base layer has a second width in the lateral direction, and the second width is greater than the first width.

公开(公告)号：US20230152518A1

公开(公告)日：2023-05-18

申请号：US17525293

申请日：2021-11-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Nicholas A. Polomoff ,  Yusheng Bian

IPC: G02B6/122

CPC classification number: G02B6/122 ,  G02B2006/12061

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photonic chip security structure and methods of manufacture. The structure includes an optical component and a photonic chip security structure having a vertical wall composed of light absorbing material surrounding the optical component.

公开(公告)号：US11637068B2

公开(公告)日：2023-04-25

申请号：US17121810

申请日：2020-12-15

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  John J. Pekarik

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00 ,  H01L23/373 ,  H01L23/48 ,  H01L27/06

Abstract: Processing forms an integrated circuit structure having first and second layers on opposite sides of an insulator, and an interconnect structure extending through the insulator between the first layer and the second layer. The interconnect structure is formed in an opening extending through the insulator between the first layer and the second layer and has an electrical conductor in the opening extending between the first layer and the second layer and a thermally conductive electrical insulator liner along sidewalls of the opening extending between the first layer and the second layer. The electrical conductor is positioned to conduct electrical signals between the first layer and the second layer, and the thermally conductive electrical insulator liner is positioned to transfer heat between the first layer and the second layer.

公开(公告)号：US20230102573A1

公开(公告)日：2023-03-30

申请号：US17586862

申请日：2022-01-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Vibhor Jain ,  Judson R. Holt

IPC: H01L29/737 ,  H01L29/735 ,  H01L29/08 ,  H01L29/66

Abstract: Disclosed is a semiconductor structure including a device, such as a lateral heterojunction bipolar transistor (HBT), made up of a combination of at least three different semiconductor materials with different bandgap sizes for improved performance. In the device, a base layer of the base region can be positioned laterally between a collector layer of a collector region and an emitter layer of an emitter region and can be physically separated therefrom by buffer layers. The base layer can be made of a narrow bandgap semiconductor material, the collector layer and, optionally, the emitter layer can be made of a wide bandgap semiconductor material, and the buffer layers can be made of a semiconductor material with a bandgap between that of the narrow bandgap semiconductor material and the wide bandgap semiconductor material. Also disclosed herein is a method of forming the structure.

公开(公告)号：US20230065924A1

公开(公告)日：2023-03-02

申请号：US17511613

申请日：2021-10-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Haiting Wang ,  Judson R. Holt ,  Vibhor Jain ,  Richard F. Taylor, III

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L21/02 ,  H01L21/225 ,  H01L29/66

Abstract: Disclosed is a semiconductor structure including a lateral heterojunction bipolar transistor (HBT). The structure includes a substrate (e.g., a silicon substrate), an insulator layer on the substrate, and a semiconductor layer (e.g., a silicon germanium layer) on the insulator layer. The structure includes a lateral HBT with three terminals including a collector, an emitter, and a base, which is positioned laterally between the collector and the emitter and which can include a silicon germanium intrinsic base region for improved performance. Additionally, the collector and/or the emitter includes: a first region, which is epitaxially grown within a trench that extends through the semiconductor layer and the insulator layer to the substrate; and a second region, which is epitaxially grown on the first region. The connection(s) of the collector and/or the emitter to the substrate effectively form thermal exit path(s) and minimize self-heating. Also disclosed is a method for forming the structure.

公开(公告)号：US20230058451A1

公开(公告)日：2023-02-23

申请号：US17450842

申请日：2021-10-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L27/12

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with a marker layer for emitter and collector terminals. A lateral bipolar transistor structure according to the disclosure includes a semiconductor layer over an insulator layer. The semiconductor layer includes an emitter/collector (E/C) region having a first doping type and an intrinsic base region adjacent the E/C region and having a second doping type opposite the first doping type. A marker layer is on the E/C region of the semiconductor layer, and a raised E/C terminal is on the marker layer. An extrinsic base is on the intrinsic base region of the semiconductor layer, and a spacer is horizontally between the raised E/C terminal and the extrinsic base.

公开(公告)号：US11581450B2

公开(公告)日：2023-02-14

申请号：US16899028

申请日：2020-06-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  Vibhor Jain ,  John J. Ellis-Monaghan

IPC: H01L31/101 ,  H01L31/107 ,  H01L31/18 ,  H01L31/0352

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one vertical pillar feature within a trench; a photosensitive semiconductor material extending laterally from sidewalls of the at least one vertical pillar feature; and a contact electrically connecting to the photosensitive semiconductor material.

公开(公告)号：US20220291126A1

公开(公告)日：2022-09-15

申请号：US17195887

申请日：2021-03-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  John J. Pekarik ,  Yusheng Bian

IPC: G01N21/64 ,  H01L31/12 ,  H01L31/02 ,  H01L31/0232 ,  G01N21/85

Abstract: A “lab on a chip” includes an optofluidic sensor and components to analyze signals from the optofluidic sensor. The optofluidic sensor includes a substrate, a channel at least partially defined by a portion of a layer of first material on the substrate, input and output fluid reservoirs in fluid communication with the channel, at least a first radiation source coupled to the substrate adapted to generate radiation in a direction toward the channel, and at least one photodiode positioned adjacent and below the channel.

公开(公告)号：US11437329B2

公开(公告)日：2022-09-06

申请号：US17070377

申请日：2020-10-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Vibhor Jain ,  Siva P. Adusumilli ,  Ajay Raman ,  Sebastian T. Ventrone ,  Yves T. Ngu

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/522 ,  H01L49/02

Abstract: The present disclosure relates to integrated circuits, and more particularly, to an anti-tamper x-ray blocking package for secure integrated circuits and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: one or more devices on a front side of a semiconductor material; a plurality of patterned metal layers under the one or more devices, located and structured to protect the one or more devices from an active intrusion; an insulator layer between the plurality of patterned metal layers; and at least one contact providing an electrical connection through the semiconductor material to a front side of the plurality of metals.