公开(公告)号：US12130470B2

公开(公告)日：2024-10-29

申请号：US17452129

申请日：2021-10-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Nicholas A. Polomoff ,  Thomas Houghton ,  Yusheng Bian

IPC: G02B6/30 ,  G02B6/12 ,  G02B6/42 ,  G02B6/43

CPC classification number: G02B6/12004 ,  G02B6/30 ,  G02B6/423 ,  G02B6/4249 ,  G02B6/43 ,  G02B2006/12061

Abstract: A photonic integrated circuit (PIC) die are provided. The PIC die includes a set of optical connect grooves including a first groove aligning a core of a first optical fiber positioned with a first optical component in a first layer at a first vertical depth in a plurality of layers of a body of the die, and a second groove aligning a core of a second optical fiber positioned therein with a second optical component in a second, different layer at a second different vertical depth in the plurality of layers. The grooves may also have end faces at different lateral depths from an edge of the body of the PIC die. Any number of the first and second grooves can be used to communicate an optical signal to any number of layers at different vertical and/or lateral depths within the body of the PIC die.

公开(公告)号：US20230228940A1

公开(公告)日：2023-07-20

申请号：US17577162

申请日：2022-01-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ian Melville ,  Nicholas Polomoff ,  Thomas Houghton ,  Koushik Ramachandran ,  Pallabi Das

IPC: G02B6/122 ,  G02B6/13

CPC classification number: G02B6/1228 ,  G02B6/13 ,  G02B2006/12061

Abstract: Structures for a cavity included in a photonics chip and methods of fabricating a structure for a cavity included in a photonics chip. The structure includes a substrate, a back-end-of-line stack having interlayer dielectric layers on the substrate, and a cavity penetrating through the back-end-of-line stack and into the substrate. The cavity includes first sidewalls and second sidewalls, and the second sidewalls have an alternating arrangement with the first sidewalls to define non-right-angle corners.

公开(公告)号：US20220268994A1

公开(公告)日：2022-08-25

申请号：US17179532

申请日：2021-02-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Asli Sahin ,  Karen A. Nummy ,  Thomas Houghton ,  Kevin K. Dezfulian ,  Kenneth J. Giewont ,  Yusheng Bian

IPC: G02B6/122 ,  G02B6/13

Abstract: A photonics integrated circuit includes a semiconductor substrate; a buried insulator layer positioned over the semiconductor substrate; and a back-end-of-line (BEOL) insulator stack over a first portion of the buried insulator layer. In addition, the PIC includes a silicon nitride (SiN) waveguide edge coupler positioned in a first region over the buried insulator layer and at least partially under the BEOL insulator stack. An oxide layer extends over a side of the BEOL insulator stack. The SiN waveguide edge coupler provides better power handling and fabrication tolerance than silicon waveguide edge couplers, despite the location under various BEOL layers. The PIC can also include silicon waveguide edger coupler(s).