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公开(公告)号：US11650381B1
公开(公告)日：2023-05-16
申请号：US17650845
申请日：2022-02-12
Applicant: GlobalFoundries U.S. Inc.
Inventor： Nicholas A. Polomoff , Yusheng Bian , Thomas Houghton
CPC classification number: G02B6/4243 , G02B6/30 , G02B6/423
Abstract: PIC die packages may include a PIC die including: a body having a plurality of layers including a plurality of interconnect layers. A first optical fiber is positioned in a groove and a second optical fiber positioned in another groove in the edge of the body. The first optical fiber is aligned with an optical component in a first layer of the body at a first vertical depth, and the second optical fiber is aligned with another optical component in a second, different layer of the body at a second different vertical depth. A cover is over at least a portion of the body. The cover includes a member having a face defining a first seat therein having a first height to receive a portion of the first optical fiber, and defining a second seat therein having a second, different height to receive a portion of the second optical fiber.
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公开(公告)号：US20220206220A1
公开(公告)日：2022-06-30
申请号：US17137549
申请日：2020-12-30
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor： Tymon Barwicz , Robert K. Leidy , Thomas Houghton
Abstract: Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The structure includes a waveguide core region on a first dielectric layer, and a second dielectric layer on the waveguide core region and the first dielectric layer. The waveguide core region has a tapered section with an end surface that terminates adjacent to an edge of the first dielectric layer. The second dielectric layer includes a first trench and a second trench that are each positioned adjacent to the tapered section of the waveguide core region.
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公开(公告)号：US20240427094A1
公开(公告)日：2024-12-26
申请号：US18212754
申请日：2023-06-22
Applicant: GlobalFoundries U.S. Inc.
Inventor： Keith Donegan , Takako Hirokawa , Yusheng Bian , Thomas Houghton , Kevin Dezfulian , Carrie Yurkon
Abstract: Structures including a calibration marker adjacent to a photonic structure and methods of forming such structures. The structure comprises a semiconductor substrate, a photonic structure, and a back-end-of-line stack over the semiconductor substrate. The back-end-of-line stack includes a plurality of fill features, an exclusion area surrounded by the plurality of fill features, and a calibration marker in the exclusion area. The calibration marker is disposed adjacent to the photonic structure, and the calibration marker includes a feature having a predetermined dimension.
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公开(公告)号：US20240402421A1
公开(公告)日：2024-12-05
申请号：US18802210
申请日：2024-08-13
Applicant: GlobalFoundries U.S. Inc.
Inventor： Nicholas A. Polomoff , Thomas Houghton , Yusheng Bian
Abstract: A photonic integrated circuit (PIC) die are provided. The PIC die includes a set of optical connect grooves including a first groove aligning a core of a first optical fiber positioned with a first optical component in a first layer at a first vertical depth in a plurality of layers of a body of the die, and a second groove aligning a core of a second optical fiber positioned therein with a second optical component in a second, different layer at a second different vertical depth in the plurality of layers. The grooves may also have end faces at different lateral depths from an edge of the body of the PIC die. Any number of the first and second grooves can be used to communicate an optical signal to any number of layers at different vertical and/or lateral depths within the body of the PIC die.
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公开(公告)号：US20210278611A1
公开(公告)日：2021-09-09
申请号：US16807811
申请日：2020-03-03
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor： Asli Sahin , Colleen Meagher , Thomas Houghton , Bo Peng , Karen Nummy , Javier Ayala , Yusheng Bian
IPC: G02B6/42 , H01L21/84 , H01L21/311
Abstract: One illustrative device disclosed herein includes a V-groove in a base semiconductor layer of a semiconductor-on-insulator (SOI) substrate, wherein the V-groove is adapted to have a fiber optics cable positioned therein, and an optical component positioned above the V-groove. The device also includes a first layer of silicon dioxide positioned above the optical component, a second layer of silicon dioxide positioned on and in contact with the first layer of silicon dioxide and a third layer of silicon dioxide positioned on and in contact with the second layer of silicon dioxide.
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Patent Agency Ranking
公开(公告)号：US20240361529A1
公开(公告)日：2024-10-31
申请号：US18139128
申请日：2023-04-25
Applicant: GlobalFoundries U.S. Inc.
Inventor： Keith Donegan , Thomas Houghton , Yusheng Bian , Karen Nummy , Kevin Dezfulian , Takako Hirokawa
CPC classification number: G02B6/305 , G02B6/42 , G02B6/4206
Abstract: Structures including a cavity adjacent to an edge coupler and methods of forming such structures. The structure comprises a semiconductor substrate including a cavity with a sidewall, a dielectric layer on the semiconductor substrate, and an edge coupler on the dielectric layer. The structure further comprises a fill region including a plurality of fill features adjacent to the edge coupler. The fill region includes a reference marker at least partially surrounded by the plurality of fill features, and the reference marker has a perimeter that surrounds a surface area of the dielectric layer, and the surface area overlaps with a portion of the sidewall of the cavity.
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公开(公告)号：US11860414B2
公开(公告)日：2024-01-02
申请号：US17137549
申请日：2020-12-30
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor： Tymon Barwicz , Robert K. Leidy , Thomas Houghton
CPC classification number: G02B6/1228 , G02B6/13
Abstract: Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The structure includes a waveguide core region on a first dielectric layer, and a second dielectric layer on the waveguide core region and the first dielectric layer. The waveguide core region has a tapered section with an end surface that terminates adjacent to an edge of the first dielectric layer. The second dielectric layer includes a first trench and a second trench that are each positioned adjacent to the tapered section of the waveguide core region.
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公开(公告)号：US11828983B2
公开(公告)日：2023-11-28
申请号：US17577162
申请日：2022-01-17
Applicant: GlobalFoundries U.S. Inc.
Inventor： Ian Melville , Nicholas Polomoff , Thomas Houghton , Koushik Ramachandran , Pallabi Das
CPC classification number: G02B6/1228 , G02B6/13 , G02B2006/12061
Abstract: Structures for a cavity included in a photonics chip and methods of fabricating a structure for a cavity included in a photonics chip. The structure includes a substrate, a back-end-of-line stack having interlayer dielectric layers on the substrate, and a cavity penetrating through the back-end-of-line stack and into the substrate. The cavity includes first sidewalls and second sidewalls, and the second sidewalls have an alternating arrangement with the first sidewalls to define non-right-angle corners.
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公开(公告)号：US20230130467A1
公开(公告)日：2023-04-27
申请号：US17452129
申请日：2021-10-25
Applicant: GlobalFoundries U.S. Inc.
Inventor： Nicholas A. Polomoff , Thomas Houghton , Yusheng Bian
Abstract: A photonic integrated circuit (PIC) die are provided. The PIC die includes a set of optical connect grooves including a first groove aligning a core of a first optical fiber positioned with a first optical component in a first layer at a first vertical depth in a plurality of layers of a body of the die, and a second groove aligning a core of a second optical fiber positioned therein with a second optical component in a second, different layer at a second different vertical depth in the plurality of layers. The grooves may also have end faces at different lateral depths from an edge of the body of the PIC die. Any number of the first and second grooves can be used to communicate an optical signal to any number of layers at different vertical and/or lateral depths within the body of the PIC die.
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公开(公告)号：US11487059B2
公开(公告)日：2022-11-01
申请号：US17179532
申请日：2021-02-19
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor： Asli Sahin , Karen A. Nummy , Thomas Houghton , Kevin K. Dezfulian , Kenneth J. Giewont , Yusheng Bian
Abstract: A photonics integrated circuit includes a semiconductor substrate; a buried insulator layer positioned over the semiconductor substrate; and a back-end-of-line (BEOL) insulator stack over a first portion of the buried insulator layer. In addition, the PIC includes a silicon nitride (SiN) waveguide edge coupler positioned in a first region over the buried insulator layer and at least partially under the BEOL insulator stack. An oxide layer extends over a side of the BEOL insulator stack. The SiN waveguide edge coupler provides better power handling and fabrication tolerance than silicon waveguide edge couplers, despite the location under various BEOL layers. The PIC can also include silicon waveguide edger coupler(s).
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