公开(公告)号：US5479130A

公开(公告)日：1995-12-26

申请号：US196597

申请日：1994-02-15

申请人： Damien McCartney

发明人： Damien McCartney

IPC分类号： G06G7/186 ,  H03F1/08

CPC分类号： G06G7/1865

摘要： A switched-capacitor auto-zero integrator includes and integrator circuit and a correction circuit. The integrator circuit may be any circuit including an operational amplifier having an input line and an output line, an input capacitor coupled to be charged by an Input voltage, an integrating capacitor coupled to the output line, and at least one integrating switch operable during an integrating time interval to connect the input capacitor to the integrating capacitor such that the integrating capacitor is charged to compensate for charge of the input capacitor. The correction circuit includes an offset capacitor coupled to the input line and at least one correction switch operable in an auto-zero sub-interval: and a correction sub-interval. The sub-intervals occur only during the integrating interval such that the offset capacitor is charged by an offset voltage and a gain error voltage of the operational amplifier during the auto-zero sub-interval and the offset capacitor is connected to a summing node between the input capacitor and the integrating capacitor during the correction sub-interval.

摘要翻译： 开关电容自动归零积分器包括积分器电路和校正电路。 积分器电路可以是包括具有输入线和输出线的运算放大器的任何电路，耦合到由输入电压充电的输入电容器，耦合到输出线的积分电容器，以及至少一个可在 积分时间间隔以将输入电容器连接到积分电容器，使得积分电容器被充电以补偿输入电容器的电荷。 校正电路包括耦合到输入线的偏移电容器和在自动归零子区间可操作的至少一个校正开关：和校正子间隔。 子间隔仅在积分间隔期间发生，使得偏移电容器在自动归零子区间期间由偏移电压和运算放大器的增益误差电压充电，并且偏移电容器连接到 输入电容器和积分电容器在校正子间隔期间。

公开(公告)号：US06268820B1

公开(公告)日：2001-07-31

申请号：US09566245

申请日：2000-05-05

申请人： Adrian Sherry ,  Damien McCartney

发明人： Adrian Sherry ,  Damien McCartney

IPC分类号： H03M112

CPC分类号： G06F3/05

摘要： An analog to digital conversion system having a plurality of analog to digital converters (ADCs). Each one of such ADCs is configured to convert a corresponding one of a plurality of analog signals into a corresponding sequence of digital words. The ADCs have different degrees of conversion performance. A source of the pulses is included. Each one of the ADCs is configured to provide a corresponding one of the sequences of digital words in response to the pulses. Each one of the digital words in each of the sequences is provided at substantially the same time. A controller is provided for interrupting and/or changing the configuration of one or more of the ADCs. The controller provides the interrupt and/or change in configuration with a priority to one of the ADCs over the other one of the ADCs.

摘要翻译： 具有多个模数转换器（ADC）的模数转换系统。 这些ADC中的每一个被配置为将多个模拟信号中的相应的一个转换成相应的数字字序列。 ADC具有不同程度的转换性能。 包括脉冲的源。 每个ADC被配置为响应于脉冲提供数字字的序列中的对应的一个。 每个序列中的每一个数字字基本相同地被提供。 提供了用于中断和/或改变一个或多个ADC的配置的控制器。 控制器提供中断和/或更改配置，优先于另一个ADC的ADC之一。

公开(公告)号：US5805091A

公开(公告)日：1998-09-08

申请号：US600314

申请日：1996-02-12

申请人： Adrian Sherry ,  Damien McCartney

发明人： Adrian Sherry ,  Damien McCartney

IPC分类号： H03M1/10 ,  H03M1/12

CPC分类号： H03M1/1076 ,  H03M1/12

摘要： An invalid reference detection circuit formed on a semiconductor chip having: reference input terminals adapted for coupling to a reference source external to the chip; a local reference source; and comparison circuit. The comparison circuit is responsive to the local reference source and a condition at the reference input terminals to detect an invalid condition at the reference input terminals and to produce an output signal indicative of the detected invalid condition. The invalid condition at the reference input terminals may be an open circuit condition at at least one of the reference input terminals, a condition when the voltage across the reference input terminals is below a predetermined minimum voltage level, a condition when the voltage across the reference input terminals is above a predetermined maximum voltage level, and/or a short circuit condition. An analog/digital conversion system is formed on a semiconductor chip together with the invalid reference detection circuit. The reference input terminals are adapted for coupling to the reference source external to the chip to the conversion circuitry to provide a reference for such conversion circuitry.

摘要翻译： 一种形成在半导体芯片上的无效参考检测电路，具有：用于耦合到芯片外部的参考源的参考输入端; 本地参考资料来源; 和比较电路。 比较电路响应于本地参考源和参考输入端的条件，以检测参考输入端的无效状态，并产生表示检测到的无效状态的输出信号。 在参考输入端子处的无效状态可以是至少一个参考输入端子处的开路状态，当参考输入端子两端的电压低于预定的最小电压电平时， 输入端子高于预定的最大电压电平和/或短路状态。 模拟/数字转换系统与无效参考检测电路一起形成在半导体芯片上。 参考输入端适于耦合到芯片外部的参考源到转换电路，为这种转换电路提供参考。

公开(公告)号：US5159341A

公开(公告)日：1992-10-27

申请号：US667818

申请日：1991-03-12

申请人： Damien McCartney ,  David R. Welland

发明人： Damien McCartney ,  David R. Welland

IPC分类号： H03M3/02

CPC分类号： H03M3/354 ,  H03M3/43 ,  H03M3/438 ,  H03M3/47

摘要： A delta sigma modulator provides dual phase sampling of analog input and/or a reference voltage. This dual phase sampling may be realized using a switched capacitor circuit having dual legs with a capacitor on each such leg. The dual phase sampling of the reference voltage poses a complication that mandates the necessity of providing a compensation signal. The delta sigma modulator is provided with appropriate circuitry to provide a compensation signal that compensates for the reduced signal level due to the dual sampling. In particular, the delta sigma modulator compensates for the reduced level of the output from an integrating amplifier circuit due to the timing necessary to implement the dual sampling approach.

摘要翻译： ΔΣ调制器提供模拟输入和/或参考电压的双相采样。 这种双相采样可以使用具有在每个这样的支路上具有电容器的双支路的开关电容器电路来实现。 参考电压的双相采样构成了需要提供补偿信号的复杂性。 ΔΣ调制器设置有适当的电路，以提供补偿信号，该补偿信号补偿由于双重采样引起的降低的信号电平。 特别地，由于执行双重采样方法所需的定时，ΔΣ调制器补偿了积分放大器电路的输出电平的降低。

公开(公告)号：US06970126B1

公开(公告)日：2005-11-29

申请号：US10876883

申请日：2004-06-25

申请人： John O'Dowd ,  Damien McCartney

发明人： John O'Dowd ,  Damien McCartney

IPC分类号： H03M1/12 ,  H03M3/02

CPC分类号： H03M3/34 ,  H03M3/43

摘要： A variable capacitance switched capacitor input system and method includes a differential integrator circuit having first and second input summing nodes and a variable sensing capacitor; one terminal of the variable sensing capacitor is connected to one of the nodes in the first phase and to the other of the nodes in the second phase; an input terminal connected to a second terminal of the variable sensing capacitor receives a first voltage level in the first phase and a second voltage level in the second phase for delivering the charge on the variable sensing capacitor to the first summing node in the first phase and to the second summing node in the second phase and canceling errors in a differential integrator circuit output caused by leakage current.

摘要翻译： 可变电容开关电容器输入系统和方法包括具有第一和第二输入求和节点的差分积分电路和可变感测电容器; 可变感测电容器的一个端子连接到第一相中的节点之一和第二相中的另一个节点; 连接到可变感测电容器的第二端子的输入端子接收第一相位中的第一电压电平和第二相位中的第二电压电平，用于将可变感测电容器上的电荷传送到第一相位中的第一求和节点;以及 到第二阶段的第二求和节点，并且消除由漏电流引起的差分积分电路输出中的误差。

公开(公告)号：US20050229710A1

公开(公告)日：2005-10-20

申请号：US10914909

申请日：2004-08-10

申请人： John O'Dowd ,  Damien McCartney ,  William Hunt ,  Eamon Hynes ,  John Wynne ,  Patrick Crowley ,  John Martin

发明人： John O'Dowd ,  Damien McCartney ,  William Hunt ,  Eamon Hynes ,  John Wynne ,  Patrick Crowley ,  John Martin

IPC分类号： G01L20060101 ,  G01L9/00 ,  G01L9/12 ,  G01L13/02

CPC分类号： G01L9/0072 ,  G01L9/0073 ,  G01L9/0075 ,  G01L13/025 ,  G01L19/0076 ,  H01L2224/48091 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： A capacitive sensor including a housing having a hermetically sealed cavity, a plate in the cavity, a diaphragm forming a part of the cavity and spaced from the plate, a conductive layer on the first diaphragm, and a second conductive layer on the plate, the first and second conductive layers being the electrodes of a capacitor whose capacitance varies with the position of the diaphragm relative to the plate.

摘要翻译： 一种电容传感器，包括具有气密密封空腔的壳体，腔体中的板，形成腔的一部分并与板隔开的隔膜，第一隔膜上的导电层和板上的第二导电层， 第一和第二导电层是电容器的电极，其电容随着隔膜相对于板的位置而变化。

公开(公告)号：US06380801B1

公开(公告)日：2002-04-30

申请号：US09589960

申请日：2000-06-08

申请人： Damien McCartney

发明人： Damien McCartney

IPC分类号： H03F102

CPC分类号： H03F3/72 ,  H03F3/3064 ,  H03F3/45219 ,  H03F3/45775 ,  H03F2203/45462 ,  H03F2203/7221

摘要： An operational amplifier having two differential input stages. A first one of the stages comprises a pair of first input transistors and another one of such stages comprises a pair of second input transistors. The second input transistors are complementary in type to the first input transistors. A comparator is fed by a sense signal and a reference signal, such sense signal being related to at least one of a non-inverting and an inverting input signal fed to the operational amplifier. The comparator produces a control signal in accordance with a difference between the sense signal and the reference signal. A switching network is responsive to the control signal and couples an output of either the first one of the stages or the second one of the stages to an output of the operational amplifier selectively in accordance with the control signal. An input chop circuit is adapted for coupling to a differential input signal, formed by the non-inverting and inverting input signals, and for providing the differential input signal with a non-inverted polarity during a first time period and such differential input signal with an inverted polarity during a succeeding time period. The differential input signal with the provided inverted polarity and the provided non-inverted polarity are fed to the coupled one of the two stages during the first time period and the succeeding time period, respectively. With such an arrangement, transitional regions where one of the stages that are coupled to the amplifier output is partially operational are eliminated, thereby reducing errors that occur in these transitional regions.

摘要翻译： 具有两个差分输入级的运算放大器。 第一级中的第一级包括一对第一输入晶体管，另外一级包括一对第二输入晶体管。 第二输入晶体管的类型与第一输入晶体管是互补的。 比较器由感测信号和参考信号馈送，这种感测信号与馈送到运算放大器的非反相和反相输入信号中的至少一个有关。 比较器根据感测信号和参考信号之间的差产生控制信号。 切换网络响应于控制信号，并且根据控制信号选择性地将级的第一级或第二级的输出耦合到运算放大器的输出。 输入斩波电路适于耦合到由非反相和反相输入信号形成的差分输入信号，并且用于在第一时间周期期间提供具有非反相极性的差分输入信号，并且该差分输入信号具有 在随后的时间段内反转极性。 具有反相极性和提供的非反相极性的差分输入信号分别在第一时间段和后续时间段期间馈送到两个耦合的一个级。 通过这样的布置，消除了耦合到放大器输出的级中的一个部分可操作的过渡区域，从而减少在这些过渡区域中发生的错误。

公开(公告)号：US06323801B1

公开(公告)日：2001-11-27

申请号：US09348951

申请日：1999-07-07

申请人： Damien McCartney ,  John O'Dowd ,  Niall McGuinness ,  John Keane

发明人： Damien McCartney ,  John O'Dowd ,  Niall McGuinness ,  John Keane

IPC分类号： H03M112

CPC分类号： H03M3/464

摘要： A method and circuit for providing a reference voltage to a charge balance circuit. The method includes transferring charge corresponding to VBE and charge corresponding to &Dgr;VBE to a summing node of the charge balance circuit, where VBE is a voltage produced across a p-n junction and where &Dgr;VBE is a difference between two VBE voltages. With such method, instead of forming a bandgap reference circuit which produces a bandgap reference voltage and applying such voltage to the reference sampling and charge transfer circuit, charge corresponding to VBE and charge corresponding to &Dgr;VBE are transferred to the input summing node of the modulator in correct proportion and with a polarity corresponding to the modulator output. Thus, the reference sampling and charge transfer circuit delivers VBE and &Dgr;VBE charge samples to the summing node having the correct proportion and polarity, that in aggregate over a modulator cycle, equal the charge that sampling the reference voltage VREF produced by the explicit bandgap reference circuits would deliver.

摘要翻译： 一种用于向电荷平衡电路提供参考电压的方法和电路。 该方法包括将对应于VBE的电荷和对应于DELTAVBE的电荷转移到电荷平衡电路的求和节点，其中VBE是在p-n结上产生的电压，其中DELTAVBE是两个VBE电压之间的差。 利用这种方法，代替形成带隙参考电压，产生带隙基准电压并将该电压施加到参考采样和电荷转移电路，而不是对应于VBE的电荷和对应于DELTAVBE的电荷被传送到调制器的输入求和节点 正确的比例和与调制器输出相对应的极性。 因此，参考采样和电荷转移电路将VBE和DELTAVBE电荷样本传递到具有正确比例和极性的求和节点，在调制器周期中的总和等于由显式带隙参考电路产生的参考电压VREF的采样电荷 会交付

公开(公告)号：US5777911A

公开(公告)日：1998-07-07

申请号：US600296

申请日：1996-02-12

申请人： Adrian Sherry ,  Damien McCartney ,  Michael Byrne

发明人： Adrian Sherry ,  Damien McCartney ,  Michael Byrne

IPC分类号： G06F17/10

CPC分类号： G06F17/10

摘要： A digital filtering system is fed by input signal and produces an output signal from either a relatively low bandwidth filter or a relatively wide bandwidth filter selectively in accordance with the time rate of change in the input signal. The output signal is produced by the relatively low bandwidth filter when the input signal is slowly varying and the output signal is produced by the relatively wide bandwidth filter when the input signal changes rapidly, after which the output is produced from the relatively low bandwidth filter when the input signal reverts to its more slowly varying characteristics.

公开(公告)号：US5745060A

公开(公告)日：1998-04-28

申请号：US600313

申请日：1996-02-12

申请人： Damien McCartney ,  John O'Dowd

发明人： Damien McCartney ,  John O'Dowd

IPC分类号： H03M3/02 ,  H03M1/10

CPC分类号： H03M3/38 ,  H03M3/43 ,  H03M3/456

摘要： A method, and apparatus, for calibrating a delta sigma modulator. The delta sigma modulator includes an integrating amplifier circuit with an integrating capacitor for producing an output indicative of an amount of charge held on the integration capacitor. During the calibration mode, a feedback signal sampling section samples a feedback signal and transfers packets of charge corresponding to such sampled feedback signal to the integrating capacitor in each modulator cycle and an input signal section samples a calibration signal and transfers packets of charge corresponding to a portion of the calibration signal to the integrating capacitor in each modulator cycle. With such an arrangement, some charge is transferred to the integration capacitor in each modulator cycle thus reducing idle-tones.

摘要翻译： 一种用于校准Δ-Σ调制器的方法和装置。 ΔΣ调制器包括具有积分电容器的积分放大器电路，用于产生指示保持在积分电容器上的电荷量的输出。 在校准模式期间，反馈信号采样部分对反馈信号进行采样，并在每个调制器周期中将与这种采样的反馈信号相对应的电荷分组传送给积分电容器，并且输入信号部分对校准信号进行采样并且传送对应于 在每个调制器周期中校准信号的一部分到积分电容器。 通过这样的布置，在每个调制器周期中将一些电荷转移到积分电容器，从而减少空闲音调。