公开(公告)号：US20230068314A1

公开(公告)日：2023-03-02

申请号：US17984170

申请日：2022-11-09

申请人： Intel Corporation

发明人： Rishabh MEHANDRU ,  Tahir GHANI ,  Stephen CEA ,  Biswajeet GUHA

IPC分类号： H01L29/775 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

摘要： Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.

公开(公告)号：US20220310601A1

公开(公告)日：2022-09-29

申请号：US17211745

申请日：2021-03-24

申请人： Intel Corporation

发明人： Aaron D. LILAK ,  Cory WEBER ,  Stephen M. CEA ,  Leonard C. PIPES ,  Seahee HWANGBO ,  Rishabh MEHANDRU ,  Patrick KEYS ,  Jack YAUNG ,  Tzu-Min OU

IPC分类号： H01L27/092 ,  H01L29/66 ,  H01L29/78

摘要： Fin doping, and integrated circuit structures resulting therefrom, are described. In an example, an integrated circuit structure includes a semiconductor fin. A lower portion of the semiconductor fin includes a region having both N-type dopants and P-type dopants with a net excess of the P-type dopants of at least 2E18 atoms/cm3. A gate stack is over and conformal with an upper portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20220093460A1

公开(公告)日：2022-03-24

申请号：US17542191

申请日：2021-12-03

申请人： Intel Corporation

发明人： Rishabh MEHANDRU

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L23/535 ,  H01L29/66

摘要： Wrap-around contact structures for semiconductor fins, and methods of fabricating wrap-around contact structures for semiconductor fins, are described. In an example, an integrated circuit structure includes a semiconductor fin having a first portion protruding through a trench isolation region. A gate structure is over a top and along sidewalls of the first portion of the semiconductor fin. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor fin. The epitaxial structure has substantially vertical sidewalls in alignment with the second portion of the semiconductor fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor fin and along the substantially vertical sidewalls of the epitaxial structure.

公开(公告)号：US20220069094A1

公开(公告)日：2022-03-03

申请号：US17522764

申请日：2021-11-09

申请人： Intel Corporation

发明人： Patrick MORROW ,  Rishabh MEHANDRU ,  Aaron D. LILAK ,  Kimin JUN

IPC分类号： H01L29/417 ,  H01L29/423 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40

摘要： An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

公开(公告)号：US20210050423A1

公开(公告)日：2021-02-18

申请号：US17085857

申请日：2020-10-30

申请人： Intel Corporation

发明人： Rishabh MEHANDRU ,  Pratik A. PATEL ,  Thomas T. TROEGER ,  Szuya S. LIAO

IPC分类号： H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/321 ,  H01L29/08 ,  H01L29/40 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

摘要： Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.

公开(公告)号：US20200176482A1

公开(公告)日：2020-06-04

申请号：US16785986

申请日：2020-02-10

申请人： Intel Corporation

发明人： Aaron D. LILAK ,  Patrick MORROW ,  Stephen M. CEA ,  Rishabh MEHANDRU ,  Cory E. WEBER

IPC分类号： H01L27/12 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3115 ,  H01L21/84

摘要： Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.

公开(公告)号：US20200006546A1

公开(公告)日：2020-01-02

申请号：US16024724

申请日：2018-06-29

申请人： Intel Corporation

发明人： Rishabh MEHANDRU ,  Tahir GHANI ,  Stephen CEA

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

摘要： A semiconductor device includes a semiconductor body that includes a surface and a first region and a second region formed in the semiconductor body, where a channel region is located between the first region and the second region, and where the second region includes a sub-region that includes a blanket dopant; a first conductive contact on the surface of the semiconductor body above the first region; a semiconductor-on-insulator (SOI) at a bottom of the first region; and a pocket channel dopant (PCD) formed in the channel, where a first portion of the PCD is adjacent to a first portion of the SOI; and a second conductive contact on a bottom portion of the sub-region, where a first portion of the second conductive contact is adjacent to a second portion of the SOI, and a second portion of the second conductive contact is adjacent to a second portion of the PCD.

公开(公告)号：US20190393214A1

公开(公告)日：2019-12-26

申请号：US16017971

申请日：2018-06-25

申请人： Intel Corporation

发明人： Aaron LILAK ,  Patrick MORROW ,  Gilbert DEWEY ,  Willy RACHMADY ,  Rishabh MEHANDRU

IPC分类号： H01L27/06 ,  H01L29/78 ,  H01L29/06 ,  H01L23/522 ,  H01L21/8234 ,  H01L21/822 ,  H01L27/02

摘要： Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a lower device layer that includes a first transistor structure, an upper device layer above the lower device layer including a second transistor structure, and an isolation wall that extends between the upper device layer and the lower device layer. The isolation wall may be in contact with an edge of a first gate structure of the first transistor structure and an edge of a second gate structure of the second transistor structure, and may have a first width to the edge of the first gate structure at the lower device layer, and a second width to the edge of the second gate structure at the upper device layer. The first width may be different from the second width. Other embodiments may be described and/or claimed.

公开(公告)号：US20240332403A1

公开(公告)日：2024-10-03

申请号：US18738693

申请日：2024-06-10

申请人： Intel Corporation

发明人： Patrick MORROW ,  Rishabh MEHANDRU ,  Aaron D. LILAK

IPC分类号： H01L29/66 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L29/66795 ,  H01L21/8221 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/0688 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/78696 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673

摘要： A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. The second device layer is revealed from the second substrate side. A first insulating layer is deposited on the revealed second device layer. A first opening is formed in the first insulating layer to expose a first portion of the second device layer. A contact region is formed on the exposed first portion of the second device layer.

公开(公告)号：US20240047566A1

公开(公告)日：2024-02-08

申请号：US18379548

申请日：2023-10-12

申请人： Intel Corporation

发明人： Rishabh MEHANDRU ,  Tahir GHANI ,  Stephen CEA ,  Biswajeet GUHA

IPC分类号： H01L29/775 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/775 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696

摘要： Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.