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29 条记录 (耗时 0.017 秒)

    Device with stepped source/drain region profile
    12.
    发明申请
    Device with stepped source/drain region profile 有权
    具有阶梯式源极/漏极区域剖面的器件

    公开(公告)号：US20060145273A1

    公开(公告)日：2006-07-06

    申请号：US11031843

    申请日：2005-01-06

    申请人： Giuseppe Curello ,  Bernhard Sell ,  Sunit Tyagi ,  Chris Auth

    发明人： Giuseppe Curello ,  Bernhard Sell ,  Sunit Tyagi ,  Chris Auth

    IPC分类号： H01L29/94

    CPC分类号： H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842

    摘要： Embodiments of the invention provide a transistor with stepped source and drain regions. The stepped regions may provide significant strain in a channel region while minimizing current leakage. The stepped regions may be formed by forming two recesses in a substrate to result in a stepped recess, and forming the source/drain regions in the recesses.

    摘要翻译： 本发明的实施例提供了具有阶梯式源极和漏极区域的晶体管。 台阶区域可以在通道区域中提供显着的应变，同时最小化电流泄漏。 可以通过在基板中形成两个凹槽来形成阶梯状区域，以形成阶梯状凹陷，并且在凹部中形成源极/漏极区域。

    Enhancing strained device performance by use of multi narrow section layout
    13.
    发明申请
    Enhancing strained device performance by use of multi narrow section layout 有权
    通过使用多窄截面布局来增强设备的应变性能

    公开(公告)号：US20050221566A1

    公开(公告)日：2005-10-06

    申请号：US10815911

    申请日：2004-03-31

    申请人： Giuseppe Curello ,  Thomas Hoffmann ,  Mark Armstrong

    发明人： Giuseppe Curello ,  Thomas Hoffmann ,  Mark Armstrong

    IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/80 ,  H01L21/336 ,  H01L31/112

    CPC分类号： H01L29/78 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/7843 ,  Y10S438/938

    摘要： A semiconductor device having high tensile stress. The semiconductor device comprises a substrate having a source region and a drain region. Each of the source region and the drain region includes a plurality of separated source sections and drain sections, respectively. A shallow trench isolation (STI) region is formed between two separated source sections of the source region and between two separated drain sections of the drain region. A gate stack is formed on the substrate. A tensile inducing layer is formed over the substrate. The tensile inducing layer covers the STI regions, the source region, the drain region, and the gate stack. The tensile inducing layer is an insulation capable of causing tensile stress in the substrate.

    摘要翻译： 具有高拉伸应力的半导体器件。 半导体器件包括具有源极区和漏极区的衬底。 源极区域和漏极区域中的每一个分别包括多个分离的源极部分和漏极部分。 在源极区的两个分离的源极部分和漏极区域的两个分离的漏极部分之间形成浅沟槽隔离（STI）区域。 在基板上形成栅叠层。 在衬底上形成拉伸诱导层。 拉伸感应层覆盖STI区域，源极区域，漏极区域和栅极叠层。 拉伸诱导层是能够在基板中引起拉伸应力的绝缘体。

    Selective spacer formation on transistors of different classes on the same device
    16.
    发明授权
    Selective spacer formation on transistors of different classes on the same device 有权
    在同一器件上的不同类晶体管上的选择性间隔物形成

    公开(公告)号：US07541239B2

    公开(公告)日：2009-06-02

    申请号：US11479762

    申请日：2006-06-30

    申请人： Giuseppe Curello ,  Ian R. Post ,  Chia-Hong Jan ,  Mark Bohr

    发明人： Giuseppe Curello ,  Ian R. Post ,  Chia-Hong Jan ,  Mark Bohr

    IPC分类号： H01L21/8238 ,  H01L31/119

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

    摘要： A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.

    摘要翻译： 在通过这种方法形成的第一类晶体管和器件上选择性地形成间隔物的方法。 该方法可以包括在其上具有不同类别的晶体管的衬底上沉积共形第一沉积层，将沉积层分隔成至少一类晶体管，干蚀刻第一沉积层，去除阻挡层，沉积保形第二沉积 在所述衬底上干燥蚀刻所述第二沉积层并湿蚀刻剩余的第一沉积层。 与第二类晶体管的间隔物相比，器件可以包括具有较大间隔物的第一类晶体管。

    Strained silicon MOS device with box layer between the source and drain regions
    18.
    发明授权
    Strained silicon MOS device with box layer between the source and drain regions 有权
    应变硅MOS器件，在源极和漏极区之间具有盒层

    公开(公告)号：US07422950B2

    公开(公告)日：2008-09-09

    申请号：US11304351

    申请日：2005-12-14

    申请人： Giuseppe Curello ,  Hemant V. Deshpande ,  Sunit Tyagi ,  Mark Bohr

    发明人： Giuseppe Curello ,  Hemant V. Deshpande ,  Sunit Tyagi ,  Mark Bohr

    IPC分类号： H01L21/84

    CPC分类号： H01L29/66628 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78687

    摘要： A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a channel region subjacent to the gate stack and disposed between the source region and the drain region. The MOS device of the invention further includes a buried oxide (BOX) region subjacent to the channel region and disposed between the source region and the drain region. The BOX region enables deeper source and drain regions to be formed to reduce transistor resistance and silicide spike defects while preventing gate edge junction parasitic capacitance.

    摘要翻译： MOS器件包括栅极堆叠，其包括设置在栅极电介质上的栅极电极，形成在栅极堆叠的横向相对侧上的第一间隔物和第二间隔物，靠近第一间隔物的源极区域，靠近第二间隔区的漏极区域 间隔物和位于栅叠层下方的沟道区，并设置在源区和漏区之间。 本发明的MOS器件还包括在沟道区域的下方并设置在源极区域和漏极区域之间的掩埋氧化物（BOX）区域。 BOX区域能够形成更深的源极和漏极区域，以减少晶体管电阻和硅化物尖峰缺陷，同时防止栅极边缘结的寄生电容。

    Strained silicon MOS device with box layer between the source and drain regions
    20.
    发明申请
    Strained silicon MOS device with box layer between the source and drain regions 有权
    应变硅MOS器件，在源极和漏极区之间具有盒层

    公开(公告)号：US20070134859A1

    公开(公告)日：2007-06-14

    申请号：US11304351

    申请日：2005-12-14

    申请人： Giuseppe Curello ,  Hemant Deshpande ,  Sunit Tyagi ,  Mark Bohr

    发明人： Giuseppe Curello ,  Hemant Deshpande ,  Sunit Tyagi ,  Mark Bohr

    IPC分类号： H01L21/84

    CPC分类号： H01L29/66628 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78687

    摘要： A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a channel region subjacent to the gate stack and disposed between the source region and the drain region. The MOS device of the invention further includes a buried oxide (BOX) region subjacent to the channel region and disposed between the source region and the drain region. The BOX region enables deeper source and drain regions to be formed to reduce transistor resistance and silicide spike defects while preventing gate edge junction parasitic capacitance.

    摘要翻译： MOS器件包括栅极堆叠，其包括设置在栅极电介质上的栅极电极，形成在栅极堆叠的横向相对侧上的第一间隔物和第二间隔物，靠近第一间隔物的源极区域，靠近第二间隔区的漏极区域 间隔物和位于栅叠层下方的沟道区，并设置在源区和漏区之间。 本发明的MOS器件还包括在沟道区域的下方并设置在源极区域和漏极区域之间的掩埋氧化物（BOX）区域。 BOX区域能够形成更深的源极和漏极区域，以减少晶体管电阻和硅化物尖峰缺陷，同时防止栅极边缘结的寄生电容。