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34 条记录 (耗时 0.039 秒)

    Memory device and method of transferring data in memory device
    11.
    发明授权
    Memory device and method of transferring data in memory device 有权
    存储器件和在存储器件中传送数据的方法

    公开(公告)号：US07242633B1

    公开(公告)日：2007-07-10

    申请号：US11044740

    申请日：2005-01-26

    申请人： Alvin Y. Ching ,  Raymond C. Pang ,  Steven P. Young ,  Thanh Pham

    发明人： Alvin Y. Ching ,  Raymond C. Pang ,  Steven P. Young ,  Thanh Pham

    IPC分类号： G11C8/00

    CPC分类号： H03K19/1776 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C15/00

    摘要： According to one aspect of the invention, a circuit for accessing data in a memory is disclosed. The circuit generally comprises a first port having a read logic circuit and a first output which generates data from the memory. A second port has a read logic circuit and a write logic circuit. A second output is coupled to the second port, and also generates data from the memory. Circuits for separately selecting read and write widths for a port of a memory, such as a random access memory, are disclosed. Finally, other embodiments related to implementing a content addressable memory in a programmable logic device are disclosed. Further, a method of accessing data in a memory is disclosed.

    摘要翻译： 根据本发明的一个方面，公开了一种用于访问存储器中的数据的电路。 电路通常包括具有读逻辑电路的第一端口和从存储器产生数据的第一输出。 第二端口具有读逻辑电路和写逻辑电路。 第二输出耦合到第二端口，并且还从存储器产生数据。 公开了用于单独选择存储器的端口（例如随机存取存储器）的读取和写入宽度的电路。 最后，公开了在可编程逻辑器件中实现内容可寻址存储器的其它实施例。 此外，公开了一种访问存储器中的数据的方法。

    Digital clock manager having cascade voltage switch logic clock paths
    12.
    发明授权
    Digital clock manager having cascade voltage switch logic clock paths 有权
    数字时钟管理器具有级联电压开关逻辑时钟路径

    公开(公告)号：US07038519B1

    公开(公告)日：2006-05-02

    申请号：US10837324

    申请日：2004-04-30

    申请人： Raymond C. Pang ,  Jennifer Wong

    发明人： Raymond C. Pang ,  Jennifer Wong

    IPC分类号： H03H11/26

    CPC分类号： H03K19/1738 ,  H03H11/26 ,  H03K2005/00195 ,  H03K2005/00228 ,  H03K2005/00234

    摘要： A digital clock manager having differential clock signal paths is provided. The differential clock signal paths are provided by replacing single-ended circuit elements of a conventional digital clock manager with symmetrical cascade voltage switch logic (CVSL) circuit elements, including CVSL delay buffers, CVSL multiplexers, CVSL AND gates, CVSL OR gates and CVSL set-reset latches. These symmetrical CVSL AND gates, CVSL OR gates and CVSL set-reset latches represent new circuit elements.

    摘要翻译： 提供具有差分时钟信号路径的数字时钟管理器。 差分时钟信号路径通过用传统数字时钟管理器的单端电路元件替代对称级联电压开关逻辑（CVSL）电路元件来提供，包括CVSL延迟缓冲器，CVSL多路复用器，CVSL与门，CVSL或门和CVSL组 - 锁存器。 这些对称的CVSL与门，CVSL或门和CVSL设置复位锁存器代表新的电路元件。

    Block RAM with configurable data width and parity for use in a field programmable gate array
    14.
    发明授权
    Block RAM with configurable data width and parity for use in a field programmable gate array 有权
    块RAM具有可配置的数据宽度和奇偶校验，用于现场可编程门阵列

    公开(公告)号：US06346825B1

    公开(公告)日：2002-02-12

    申请号：US09680205

    申请日：2000-10-06

    申请人： Raymond C. Pang ,  Steven P. Young ,  Trevor J. Bauer

    发明人： Raymond C. Pang ,  Steven P. Young ,  Trevor J. Bauer

    IPC分类号： H03K19177

    CPC分类号： H03K19/1776

    摘要： A dedicated block random access memory (RAM) is provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA). The block RAM includes a memory cell array and control logic that is configurable to select one of a plurality of parity or non-parity modes for accessing the memory cell array. In one embodiment, the non-parity modes include a 1×16384 mode, a 2×8192 mode, and a 4×4096 mode, while the parity modes include a 9×2048 mode, a 18×1024 mode and an 36×512 mode. The control logic selects the parity/non-parity mode in response to configuration bits stored in corresponding configuration memory cells of the PLD. The configuration bits are programmed during configuration of the PLD. In one variation, the control logic selects the parity/non-parity mode in response to user signals. In a particular embodiment, the block RAM is a dual-port memory having a first port and a second port. In this embodiment, the first and second ports can be independently configured to have different (or the same) parity or non-parity modes.

    摘要翻译： 为诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）提供专用块随机存取存储器（RAM）。 块RAM包括存储单元阵列和控制逻辑，可配置为选择用于访问存储单元阵列的多个奇偶校验或非奇偶校验模式之一。 在一个实施例中，非奇偶校验模式包括1x16384模式，2x8192模式和4×4096模式，而奇偶校验模式包括9×2048模式，18×1024模式和36×512模式。 响应于存储在PLD的相应配置存储器单元中的配置位，控制逻辑选择奇偶校验/非奇偶校验模式。 在配置PLD期间对配置位进行编程。 在一个变化中，控制逻辑响应于用户信号选择奇偶校验/非奇偶校验模式。 在特定实施例中，块RAM是具有第一端口和第二端口的双端口存储器。 在该实施例中，第一和第二端口可以被独立地配置为具有不同的（或相同的）奇偶校验或非奇偶校验模式。

    Multi-product die configurable as two or more programmable integrated circuits of different logic capacities
    16.
    发明授权
    Multi-product die configurable as two or more programmable integrated circuits of different logic capacities 有权
    多产品管芯可配置为具有不同逻辑容量的两个或多个可编程集成电路

    公开(公告)号：US07345507B1

    公开(公告)日：2008-03-18

    申请号：US11333991

    申请日：2006-01-17

    申请人： Steven P. Young ,  Trevor J. Bauer ,  F. Erich Goetting ,  P. Hugo Lamarche ,  Patrick J. McGuire ,  Kwansuhk Oh ,  Raymond C. Pang ,  Bruce E. Talley ,  Paul Ying-Fung Wu

    发明人： Steven P. Young ,  Trevor J. Bauer ,  F. Erich Goetting ,  P. Hugo Lamarche ,  Patrick J. McGuire ,  Kwansuhk Oh ,  Raymond C. Pang ,  Bruce E. Talley ,  Paul Ying-Fung Wu

    IPC分类号： H01L25/00

    CPC分类号： H03K19/177

    摘要： A multi-product integrated circuit die includes at least two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A selection code storage circuit stores a product selection code. A first value of the product selection code selects the option where both the first and second portions of the first die are operational. A second value of the product selection code selects the option where only the first portion of the first die is operational. The selection code storage circuit can include non-volatile memory or a fuse structure, or the product selection code can be configured as a package bonding option. The product selection code can also enable boundary scan for the operational portion of the die, and omit from the boundary scan chain any portions of the die that are deliberately rendered non-operational.

    摘要翻译： 多产品集成电路管芯包括至少两个不同的部分，其中至少一个部分可以以某种方式（例如，非功能的，不可访问的和/或不可编程的）被故意地变为不可操作的。 选择码存储电路存储产品选择码。 产品选择代码的第一个值选择第一模具的第一和第二部分都可操作的选项。 产品选择代码的第二个值选择仅第一个模具的第一部分可操作的选项。 选择代码存储电路可以包括非易失性存储器或熔丝结构，或者可以将产品选择代码配置为封装绑定选项。 产品选择代码还可以为模具的操作部分启用边界扫描，并且从边界扫描链中省略故意使其不可操作的模具的任何部分。

    Circuit for and method of implementing a content addressable memory in a programmable logic device
    17.
    发明授权
    Circuit for and method of implementing a content addressable memory in a programmable logic device 有权
    在可编程逻辑器件中实现内容可寻址存储器的电路和方法

    公开(公告)号：US07248491B1

    公开(公告)日：2007-07-24

    申请号：US11044746

    申请日：2005-01-26

    申请人： Alvin Y. Ching ,  Raymond C. Pang ,  Steven P. Young ,  Thanh Pham

    发明人： Alvin Y. Ching ,  Raymond C. Pang ,  Steven P. Young ,  Thanh Pham

    IPC分类号： G11C15/00

    CPC分类号： G11C15/04 ,  G11C7/1075

    摘要： According to one aspect of the invention, a circuit for accessing data in a memory is disclosed. The circuit generally comprises a first port having a read logic circuit and a first output which generates data from the memory. A second port has a read logic circuit and a write logic circuit. A second output is coupled to the second port, and also generates data from the memory. Circuits for separately selecting read and write widths for a port of a memory, such as a random access memory, are disclosed. Finally, other embodiments related to implementing a content addressable memory in a programmable logic device are disclosed. Further, a method of accessing data in a memory is disclosed.

    摘要翻译： 根据本发明的一个方面，公开了一种用于访问存储器中的数据的电路。 电路通常包括具有读逻辑电路的第一端口和从存储器产生数据的第一输出。 第二端口具有读逻辑电路和写逻辑电路。 第二输出耦合到第二端口，并且还从存储器产生数据。 公开了用于单独选择存储器的端口（例如随机存取存储器）的读取和写入宽度的电路。 最后，公开了在可编程逻辑器件中实现内容可寻址存储器的其它实施例。 此外，公开了一种访问存储器中的数据的方法。

    Programmable logic device with decryption and structure for preventing design relocation
    18.
    发明授权
    Programmable logic device with decryption and structure for preventing design relocation 有权
    具有解密和结构的可编程逻辑器件，用于防止设计重新定位

    公开(公告)号：US07117372B1

    公开(公告)日：2006-10-03

    申请号：US09724972

    申请日：2000-11-28

    申请人： Stephen M. Trimberger ,  Raymond C. Pang ,  Walter N. Sze ,  Jennifer Wong

    发明人： Stephen M. Trimberger ,  Raymond C. Pang ,  Walter N. Sze ,  Jennifer Wong

    IPC分类号： H04L9/14 ,  H04K1/00

    CPC分类号： G01R31/31719 ,  G06F12/1408 ,  G06F21/76 ,  H04L9/0625 ,  H04L9/0637

    摘要： It is sometimes desirable to protect a design used in a PLD from being copied. According to the present invention, the design is encrypted, then loaded into a PLD, then decrypted, and then loaded into the configuration memory of the PLD. An attacker could relocate the design to a visible part of the PLD and learn the design. The present invention prevents design relocation by attaching address information to the encryption key or by encrypting an address where the design is to be loaded as well as encrypting the design itself. Thus, if an attacker tries to load the design into a different part of the PLD, the encrypted design will not decrypt properly.

    摘要翻译： 有时期望保护PLD中使用的设计不被复制。 根据本发明，设计被加密，然后加载到PLD中，然后解密，然后加载到PLD的配置存储器中。 攻击者可以将设计重新定位到PLD的可见部分，并学习设计。 本发明通过将地址信息附加到加密密钥或通过加密设计要加载的地址以及加密设计本身来防止设计重定位。 因此，如果攻击者试图将设计加载到PLD的不同部分，则加密的设计将无法正确解密。

    Structure and method for loading encryption keys through a test access port
    19.
    发明授权
    Structure and method for loading encryption keys through a test access port 有权
    通过测试访问端口加载加密密钥的结构和方法

    公开(公告)号：US06965675B1

    公开(公告)日：2005-11-15

    申请号：US09724865

    申请日：2000-11-28

    申请人： Stephen M. Trimberger ,  Raymond C. Pang ,  John M. Thendean

    发明人： Stephen M. Trimberger ,  Raymond C. Pang ,  John M. Thendean

    IPC分类号： G06F21/00 ,  H04L9/08

    CPC分类号： G06F21/76 ,  H04L9/0637 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/34

    摘要： It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being written into the PLD. It is desirable that decryption keys be stored within the PLD, and that they be loaded conveniently before a board including the PLD is sold. The invention allows the PLD to be placed into a printed circuit board and the board to be tested using a JTAG port of the PLD, and then allows the decryption keys to be loaded into a key memory using the JTAG port. Loading of the keys can be performed without also loading of a design into the PLD. Loading may be performed without the use of a device programmer.

    摘要翻译： 有时需要加密设计以加载到PLD中，以便攻击者可能不会在将设计写入PLD时学习和复制设计。 希望解密密钥存储在PLD中，并且在出售包括PLD的板之前方便地加载它们。 本发明允许使用PLD的JTAG端口将PLD放入印刷电路板和要测试的板，然后使用JTAG端口将解密密钥加载到密钥存储器中。 可以在不将设计加载到PLD中的情况下执行加载键。 可以在不使用设备编程器的情况下执行加载。