公开(公告)号：US20180308752A1

公开(公告)日：2018-10-25

申请号：US15494762

申请日：2017-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Frank W. Mont ,  Sean X. Lin ,  Mark V. Raymond

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L23/528

CPC classification number: H01L21/76895 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76883 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53242 ,  H01L23/535

Abstract: Interconnect structures and methods of forming interconnect structures. An opening is formed that penetrates from a top surface of a dielectric layer into the dielectric layer. A first conductor layer is conformally deposited with a uniform thickness on the dielectric layer surrounding the first opening. A second conductor layer is formed in a space inside the first opening that is interior of the first conductor layer. The first conductor layer and the second conductor layer collectively define a hybrid feature that is embedded in the dielectric layer.

公开(公告)号：US08932934B2

公开(公告)日：2015-01-13

申请号：US13903283

申请日：2013-05-28

Applicant: GlobalFoundries Inc.

Inventor： Moosung M. Chae ,  Errol Todd Ryan ,  Nicholas Vincent Licausi ,  Christian Witt ,  Ailian Zhao ,  Ming He ,  Sean X. Lin ,  Xunyuan Zhang ,  Kunaljeet Tanwar

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/48 ,  H01L21/316 ,  H01L21/02

CPC classification number: H01L21/76831 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76843 ,  H01L2221/1047

Abstract: A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench.

Abstract translation: 提供了一种用于在半导体制造期间减少超低k层的自形成势垒的污染的方法的方法。 一方面，一种方法包括：提供包含至少一个沟槽的固化的超低k膜，并且用孔填充材料填充膜的孔; 在沟槽的表面去除暴露的孔隙填充材料以形成暴露的孔; 并在沟槽的表面上形成自形成阻挡层。

公开(公告)号：US20140252616A1

公开(公告)日：2014-09-11

申请号：US13785934

申请日：2013-03-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sean X. Lin ,  Xunyuan Zhang ,  Ming HE ,  Larry Zhao ,  John Iacoponi ,  Kunaljeet Tanwar

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76847 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A trench in an inter-layer dielectric formed on a semiconductor substrate is defined by a bottom and sidewalls. A copper barrier lines the trench with a copper-growth-promoting liner over the barrier. The trench has bulk copper filling it, and includes voids in the copper. The copper with voids is removed, including from the sidewalls, leaving a void-free copper portion at the bottom. Immersion in an electroless copper bath promotes upward growth of copper on top of the void-free copper portion without inward sidewall copper growth, resulting in a void-free copper fill of the trench.

Abstract translation: 在半导体衬底上形成的层间电介质中的沟槽由底部和侧壁限定。 铜屏障通过屏障上的铜生长促进衬里将沟槽排列。 沟槽有大量铜填充，并且在铜中包括空隙。 具有空隙的铜被除去，包括从侧壁，在底部留下无空隙的铜部分。 浸没在无电解铜浴中促进铜在无空隙铜部分顶部的向上生长，而不会向内侧壁铜生长，导致沟槽的无空隙铜填充。

公开(公告)号：US08778789B2

公开(公告)日：2014-07-15

申请号：US13689844

申请日：2012-11-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Paul R. Besser ,  Sean X. Lin ,  Valli Arunachalam

IPC: H01L21/3205

CPC classification number: H01L29/66666 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Methods for fabricating integrated circuits having low resistance metal gate structures are provided. One method includes forming a metal gate stack in a FET trench formed in a FET region. The metal gate stack is etched to form a recessed metal gate stack and a recess. The recess is defined by sidewalls in the FET region and is disposed above the recessed metal gate stack. A liner is formed overlying the sidewalls and the recessed metal gate stack and defines an inner cavity in the recess. A copper layer is formed overlying the liner and at least partially fills the inner cavity. The copper layer is etched to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity. Copper is electrolessly deposited on the copper portion to fill a remaining portion of the inner cavity.

Abstract translation: 提供了具有低电阻金属栅极结构的集成电路制造方法。 一种方法包括在FET区域中形成的FET沟槽中形成金属栅叠层。 金属栅极堆叠被蚀刻以形成凹陷的金属栅极堆叠和凹陷。 凹槽由FET区域中的侧壁限定，并设置在凹陷金属栅极堆叠的上方。 衬套形成在侧壁和凹入的金属门叠层之上，并且在凹槽中限定内腔。 铜层形成在衬垫上方并且至少部分地填充内腔。 蚀刻铜层以露出衬套的上部，同时留下设置在内腔的底部中的铜部分。 铜无电沉积在铜部分上以填充内腔的剩余部分。