公开(公告)号：US10056292B2

公开(公告)日：2018-08-21

申请号：US15359037

申请日：2016-11-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shao Beng Law ,  Genevieve Beique ,  Frank W. Mont ,  Lei Sun ,  Xunyuan Zhang

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/76816 ,  H01L21/0337

Abstract: Methods of lithographic patterning. A metal hardmask layer is formed on a dielectric layer and a patterned layer is formed on the metal hardmask layer. A metal layer is formed on an area of the metal hardmask layer exposed by an opening in the patterned layer. After the metal layer is formed, the patterned layer is removed from the metal hardmask layer. After the patterned layer is removed, the metal hardmask layer is patterned with the metal layer masking the metal hardmask layer over the area.

公开(公告)号：US20180130699A1

公开(公告)日：2018-05-10

申请号：US15345882

申请日：2016-11-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Frank W. Mont ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76813 ,  H01L21/76808 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53257

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer with one or more wiring structures, located above the first wiring layer; a skip via with metallization, which passes through upper wiring levels including the second wiring layer and which makes contact with the one or more wiring structures of the first wiring layer; and a via structure which comprises a protective material and contacts at least one of the one or more wiring structures at the upper wiring level.

公开(公告)号：US09831174B1

公开(公告)日：2017-11-28

申请号：US15168899

申请日：2016-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Frank W. Mont ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/52 ,  H01L23/528 ,  H01L23/522 ,  H01L21/02 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L23/5226 ,  H01L21/02244 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/768 ,  H01L21/7682 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76864 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53252 ,  H01L23/53295

Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

公开(公告)号：US20200083040A1

公开(公告)日：2020-03-12

申请号：US16123042

申请日：2018-09-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Frank W. Mont ,  Han You ,  Shariq Siddiqui ,  Brown C. Peethala

IPC: H01L21/02 ,  H01L21/285

Abstract: One illustrative method disclosed includes, among other things, forming a first dielectric layer and forming first and second conductive structures comprising cobalt embedded in the first dielectric layer. A second dielectric layer is formed above and contacting the first dielectric layer. The first and second dielectric layers comprise different materials, and a portion of the second dielectric layer comprises carbon or nitrogen. A first cap layer is formed above the first and second conductive structures and the second dielectric layer.

公开(公告)号：US20190221473A1

公开(公告)日：2019-07-18

申请号：US16364465

申请日：2019-03-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Frank W. Mont ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76813 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53257 ,  H01L23/53295

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer with one or more wiring structures, located above the first wiring layer; a skip via with metallization, which passes through upper wiring levels including the second wiring layer and which makes contact with the one or more wiring structures of the first wiring layer; and a via structure which comprises a protective material and contacts at least one of the one or more wiring structures at the upper wiring level.

公开(公告)号：US20180342454A1

公开(公告)日：2018-11-29

申请号：US15602801

申请日：2017-05-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Dongfei Pei ,  Frank W. Mont

IPC: H01L23/528 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/288 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/0332 ,  H01L21/288 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53242

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a plurality of openings in a hardmask material; blocking at least one of the plurality of openings of the hardmask material with a blocking material; etching a skip via to a metallization feature in a stack of metallization features through another of the plurality of openings which is not blocked by the blocking material; and at least partially filling the skip via by a bottom up fill process.

公开(公告)号：US10056291B2

公开(公告)日：2018-08-21

申请号：US15360255

申请日：2016-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shao Beng Law ,  Xunyuan Zhang ,  Frank W. Mont ,  Genevieve Beique ,  Lei Sun

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/027 ,  H01L23/528 ,  H01L21/3205 ,  H01L21/285

CPC classification number: H01L21/76816

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to post spacer self-aligned cut structures and methods of manufacture. The method includes: providing a non-mandrel cut; providing a mandrel cut; forming blocking material on underlying conductive material in the non-mandrel cut and the mandrel cut; forming trenches with the blocking material acting as a blocking mask at the mandrel cut and the non-mandrel cut; and filling the trenches with metallization features such that the metallization features have a tip to tip alignment.

公开(公告)号：US09799559B1

公开(公告)日：2017-10-24

申请号：US15158827

申请日：2016-05-19

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Shariq Siddiqui ,  Frank W. Mont ,  Xunyuan Zhang ,  Brown Peethala ,  Douglas M. Trickett

IPC: H01L21/768 ,  H01L21/44 ,  H01L21/311 ,  H01L21/302 ,  H01L21/475 ,  H01L21/469 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/7688 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53219 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266

Abstract: A method includes, for example, providing an intermediate semiconductor structure comprising a metallic layer, a patternable layer disposed over the metallic layer, and a hard mask disposed over the patternable layer, the intermediate semiconductor structure comprising a plurality of vias extending through the hard mask onto the metallic layer, depositing a sacrificial barrier layer over the intermediate semiconductor structure and in the plurality of vias, removing a portion of the sacrificial barrier layer between the plurality of vias while maintaining a portion of the sacrificial barrier layer in the plurality of vias, forming a trench in the patternable layer between the removed portion of the sacrificial barrier layer and the plurality of vias, and removing the remaining portions of the sacrificial barrier layer from the plurality of vias.

公开(公告)号：US10157833B1

公开(公告)日：2018-12-18

申请号：US15602801

申请日：2017-05-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Dongfei Pei ,  Frank W. Mont

IPC: H01L29/40 ,  H01L23/528 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/288 ,  H01L23/532 ,  H01L23/522

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a plurality of openings in a hardmask material; blocking at least one of the plurality of openings of the hardmask material with a blocking material; etching a skip via to a metallization feature in a stack of metallization features through another of the plurality of openings which is not blocked by the blocking material; and at least partially filling the skip via by a bottom up fill process.

公开(公告)号：US20180308752A1

公开(公告)日：2018-10-25

申请号：US15494762

申请日：2017-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Frank W. Mont ,  Sean X. Lin ,  Mark V. Raymond

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L23/528

CPC classification number: H01L21/76895 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76883 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53242 ,  H01L23/535

Abstract: Interconnect structures and methods of forming interconnect structures. An opening is formed that penetrates from a top surface of a dielectric layer into the dielectric layer. A first conductor layer is conformally deposited with a uniform thickness on the dielectric layer surrounding the first opening. A second conductor layer is formed in a space inside the first opening that is interior of the first conductor layer. The first conductor layer and the second conductor layer collectively define a hybrid feature that is embedded in the dielectric layer.