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公开(公告)号:US11437568B2
公开(公告)日:2022-09-06
申请号:US16836434
申请日:2020-03-31
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Yanping Shen , Haiting Wang , Sipeng Gu
Abstract: One illustrative memory cell disclosed herein includes at least one layer of insulating material having a first opening and an internal sidewall spacer positioned within the first opening, wherein the internal sidewall spacer includes a spacer opening. The memory cell also includes a bottom electrode positioned within the spacer opening, a memory state material positioned above an upper surface of the bottom electrode and above an upper surface of the internal sidewall spacer, and a top electrode positioned above the memory state material.
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12.
公开(公告)号:US11164795B2
公开(公告)日:2021-11-02
申请号:US16828273
申请日:2020-03-24
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Sipeng Gu , Judson Holt , Haiting Wang , Bangun Indajang
IPC: H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/08
Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. First and second gate structures extend over the semiconductor body. A source/drain region is positioned laterally between the first gate structure and the second gate structure. The source/drain region includes a semiconductor layer having a first section, a second section, and a third section. A first portion of the semiconductor body is positioned between the first section of the semiconductor layer and the second section of the semiconductor layer. A second portion of the semiconductor body is positioned between the second section of the semiconductor layer and the third section of the semiconductor layer.
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13.
公开(公告)号:US20210305103A1
公开(公告)日:2021-09-30
申请号:US16828273
申请日:2020-03-24
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Sipeng Gu , Judson Holt , Haiting Wang , Bangun Indajang
IPC: H01L21/8238 , H01L27/092 , H01L29/08 , H01L29/10
Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. First and second gate structures extend over the semiconductor body. A source/drain region is positioned laterally between the first gate structure and the second gate structure. The source/drain region includes a semiconductor layer having a first section, a second section, and a third section. A first portion of the semiconductor body is positioned between the first section of the semiconductor layer and the second section of the semiconductor layer. A second portion of the semiconductor body is positioned between the second section of the semiconductor layer and the third section of the semiconductor layer.
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公开(公告)号:US20210288182A1
公开(公告)日:2021-09-16
申请号:US16819832
申请日:2020-03-16
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Sipeng Gu , Judson Holt , Haiting Wang
Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. First and second gate structures extend over the semiconductor body, a second gate structure that extends over the semiconductor body. A source/drain region is positioned laterally between the first gate structure and the second gate structure. The source/drain region includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer has a first section and a second section. The second semiconductor layer is positioned laterally between the first section of the first semiconductor layer and the second section of the first semiconductor layer.
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公开(公告)号:US20210249508A1
公开(公告)日:2021-08-12
申请号:US17243832
申请日:2021-04-29
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Jiehui Shu , Baofu Zhu , Haiting Wang , Sipeng Gu
IPC: H01L29/08 , H01L27/092 , H01L21/8238 , H01L29/78 , H01L29/66
Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.
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公开(公告)号:US20210242344A1
公开(公告)日:2021-08-05
申请号:US16781236
申请日:2020-02-04
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Haiting Wang , Sipeng Gu , Jiehui Shu , Baofu Zhu
Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a channel region in a semiconductor body. The gate structure has a first side surface and a second side surface opposite the first side surface. A first source/drain region is positioned adjacent to the first side surface of the gate structure and a second source/drain region is positioned adjacent to the second side surface of the gate structure. The first source/drain region includes a first epitaxial semiconductor layer, and the second source/drain region includes a second epitaxial semiconductor layer. A first top surface of the first epitaxial semiconductor layer is positioned at a first distance from the channel region, a second top surface of the second epitaxial semiconductor layer is positioned at a second distance from the channel region, and the first distance is greater than the second distance.
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公开(公告)号:US11075268B2
公开(公告)日:2021-07-27
申请号:US16541600
申请日:2019-08-15
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Jiehui Shu , Baofu Zhu , Haiting Wang , Sipeng Gu
IPC: H01L29/08 , H01L29/66 , H01L27/092 , H01L21/8238 , H01L29/78
Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.
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公开(公告)号:US11043566B2
公开(公告)日:2021-06-22
申请号:US16599116
申请日:2019-10-10
Applicant: GLOBALFOUNDRIES U.S. INC.
Inventor: Jiehui Shu , Judson Robert Holt , Sipeng Gu , Haiting Wang
IPC: H01L29/423 , H01L21/8234 , H01L27/088 , H01L29/417
Abstract: A semiconductor device is provided that includes a substrate, an active region, a pair of gates, a plurality of semiconductor structures and a plurality of pillar structures. The active region is over the substrate. The pair of gates is formed over the active region, and each gate of the pair of gates includes a gate structure and a pair of spacer structures disposed on sidewalls of the gate structure. The plurality of semiconductor structures is arranged between the pair of gates in an alternating arrangement configuration having a first width and a second width. The first width is substantially equal to a width of the gate structure. The plurality of semiconductor structures is separated by the plurality of pillar structures.
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公开(公告)号:US11785860B2
公开(公告)日:2023-10-10
申请号:US16846497
申请日:2020-04-13
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Sipeng Gu , Haiting Wang , Yanping Shen
IPC: H10N50/80 , H10B51/30 , H10B53/30 , H10B61/00 , H10B63/00 , H10N50/01 , H10N50/10 , H10N70/00 , H10N70/20
CPC classification number: H10N50/80 , H10B51/30 , H10B53/30 , H10B61/00 , H10B63/00 , H10N50/01 , H10N50/10 , H10N70/011 , H10N70/231 , H10N70/841
Abstract: One illustrative device disclosed herein includes a memory cell positioned in a first opening in at least one layer of insulating material. The memory cell comprises a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening, wherein the internal sidewall spacer defines a spacer opening. The device also comprises a top electrode positioned within the spacer opening.
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公开(公告)号:US11569437B2
公开(公告)日:2023-01-31
申请号:US16855745
申请日:2020-04-22
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Yanping Shen , Halting Wang , Sipeng Gu
IPC: H01L43/02 , H01L27/24 , H01L27/22 , H01L27/1159 , H01L43/08 , H01L45/00 , H01L43/12 , H01L43/10
Abstract: An illustrative device disclosed herein includes at least one layer of insulating material, a conductive contact structure having a conductive line portion and a conductive via portion and a memory cell positioned in a first opening in the at least one layer of insulating material. In this illustrative example, the memory cell includes a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening and above at least a portion of the memory state material, wherein the internal sidewall spacer defines a spacer opening and wherein the conductive via portion is positioned within the spacer opening and above a portion of the memory state material.
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