-
公开(公告)号：US20240162050A1
公开(公告)日：2024-05-16
申请号：US18516711
申请日：2023-11-21
Applicant: Google LLC
Inventor： Evan Jeffrey , Joshua Yousouf Mutus
IPC: H01L21/48 , G06N10/00 , H01L23/498 , H01L33/06
CPC classification number: H01L21/4857 , G06N10/00 , H01L23/49822 , H01L33/06
Abstract: A method of fabricating a carrier chip for distributing signals among circuit elements of a quantum computing device, includes: providing a multilayer wiring stack, the multilayer wiring stack comprising alternating layers of dielectric material and wiring; bonding a capping layer to the multilayer wiring stack, in which the capping layer includes a single crystal silicon dielectric layer; forming a via hole within the capping layer, in which the via hole extends to a first wiring layer of the multilayer wiring stack; forming an electrically conductive via within the via hole and electrically coupled to the first wiring layer; and forming a circuit element on a surface of the capping layer, in which the circuit element is directly electrically coupled to the electrically conductive via.
-
公开(公告)号：US20240126970A1
公开(公告)日：2024-04-18
申请号：US18341495
申请日：2023-06-26
Applicant: Google LLC
Inventor： Evan Jeffrey , Julian Shaw Kelly , Joshua Yousouf Mutus
IPC: G06F30/39
CPC classification number: G06F30/39 , G06F2111/02
Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for parameterization of physical dimensions of discrete circuit components for component definitions that define discrete circuit components. The component definitions may be selected for use in a device design. When a parametrization of a particular version of a discrete circuit component definition is changed, the version level of the device design is also changed and the circuit layout for the device design is physically verified for the new version level.
-
公开(公告)号：US11854833B2
公开(公告)日：2023-12-26
申请号：US17263619
申请日：2018-07-30
Applicant: Google LLC
Inventor： Evan Jeffrey , Joshua Yousouf Mutus
IPC: H01L21/48 , G06N10/00 , H01L23/498 , H01L33/06
CPC classification number: H01L21/4857 , G06N10/00 , H01L23/49822 , H01L33/06
Abstract: A method of fabricating a carrier chip for distributing signals among circuit elements of a quantum computing device, includes: providing a multilayer wiring stack, the multilayer wiring stack comprising alternating layers of dielectric material and wiring; bonding a capping layer to the multilayer wiring stack, in which the capping layer includes a single crystal silicon dielectric layer; forming a via hole within the capping layer, in which the via hole extends to a first wiring layer of the multilayer wiring stack; forming an electrically conductive via within the via hole and electrically coupled to the first wiring layer; and forming a circuit element on a surface of the capping layer, in which the circuit element is directly electrically coupled to the electrically conductive via.
-
公开(公告)号：US11271280B2
公开(公告)日：2022-03-08
申请号：US16772496
申请日：2017-12-15
Applicant: Google LLC
Inventor： Evan Jeffrey , Julian Shaw Kelly
Abstract: An apparatus includes: a transmission line resonator; and multiple resonators coupled to the transmission line resonator, in which each resonator of the multiple resonators is coupled to the transmission line resonator at a different position X along a length of the transmission line resonator, and in which, for each resonator of the multiple resonators, a coupling position Y along a length of the resonator is selected such that, upon application of a source potential to the resonator, a standing wave established in the resonator is impedance and phase matched to a standing wave established in the transmission line resonator.
-
公开(公告)号：US20200321506A1
公开(公告)日：2020-10-08
申请号：US16753431
申请日：2017-10-05
Applicant: Google LLC
Inventor： Julian Shaw Kelly , Evan Jeffrey
Abstract: A device includes a first substrate having a principal surface; a second substrate having a principal surface, in which the first substrate is bump-bonded to the second substrate such that the principal surface of the first substrate faces the principal surface of the second substrate; a circuit element having a microwave frequency resonance mode, in which a first portion of the circuit element is arranged on the principal surface of the first substrate and a second portion of the circuit element is arranged on the principal surface of the second substrate; and a first bump bond connected to the first portion of the circuit element and to the second portion of the circuit element, in which the first superconductor bump bond provides an electrical connection between the first portion and the second portion.
-
Patent Agency Ranking
公开(公告)号：US11991934B1
公开(公告)日：2024-05-21
申请号：US18088144
申请日：2022-12-23
Applicant: Google LLC
Inventor： Evan Jeffrey , Julian Shaw Kelly
CPC classification number: H10N60/815 , B82Y10/00 , G06F30/392 , G06N10/00 , H01L24/16 , H01L24/17 , H10N69/00 , H01L2224/14179 , H01L2224/16148 , H01L2224/17179
Abstract: A quantum processor includes: a first chip comprising a qubit array, in which a plurality of qubits within the qubit array define an enclosed region on the first chip, in which each qubit of the plurality of qubits that define the enclosed region is arranged to directly electromagnetically couple to an adjacent qubit of the plurality of qubits that define the enclosed region, and in which each qubit of the qubit array comprises at least two superconductor islands, and a second chip bonded to the first chip, the second chip including one or more qubit control elements, in which the qubit control elements are positioned directly over the enclosed region of the first chip.
-
公开(公告)号：US20230056318A1
公开(公告)日：2023-02-23
申请号：US17902360
申请日：2022-09-02
Applicant: Google LLC
Inventor： Julian Shaw Kelly , Evan Jeffrey
Abstract: A device includes a first substrate having a principal surface; a second substrate having a principal surface, in which the first substrate is bump-bonded to the second substrate such that the principal surface of the first substrate faces the principal surface of the second substrate; a circuit element having a microwave frequency resonance mode, in which a first portion of the circuit element is arranged on the principal surface of the first substrate and a second portion of the circuit element is arranged on the principal surface of the second substrate; and a first bump bond connected to the first portion of the circuit element and to the second portion of the circuit element, in which the first superconductor bump bond provides an electrical connection between the first portion and the second portion.
-
公开(公告)号：US20210294955A1
公开(公告)日：2021-09-23
申请号：US17340825
申请日：2021-06-07
Applicant: Google LLC
Inventor： Evan Jeffrey , Julian Shaw Kelly , Joshua Yousouf Mutus
IPC: G06F30/39
Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for parameterization of physical dimensions of discrete circuit components for component definitions that define discrete circuit components. The component definitions may be selected for use in a device design. When a parametrization of a particular version of a discrete circuit component definition is changed, the version level of the device design is also changed and the circuit layout for the device design is physically verified for the new version level.
-
公开(公告)号：US11062073B2
公开(公告)日：2021-07-13
申请号：US16470593
申请日：2016-12-23
Applicant: Google LLC
Inventor： Evan Jeffrey , Julian Shaw Kelly , Joshua Yousouf Mutus
IPC: G06F30/39 , G06F30/327 , G06F30/33 , G06F30/337 , G06F30/392 , G06F30/398 , G06F111/02 , G06F111/04
Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for parameterization of physical dimensions of discrete circuit components for component definitions that define discrete circuit components. The component definitions may be selected for use in a device design. When a parametrization of a particular version of a discrete circuit component definition is changed, the version level of the device design is also changed and the circuit layout for the device design is physically verified for the new version level.
-
公开(公告)号：US20210175095A1
公开(公告)日：2021-06-10
申请号：US17263619
申请日：2018-07-30
Applicant: Google LLC
Inventor： Evan Jeffrey , Joshua Yousouf Mutus
IPC: H01L21/48 , G06N10/00 , H01L23/498 , H01L33/06
Abstract: A method of fabricating a carrier chip for distributing signals among circuit elements of a quantum computing device, includes: providing a multilayer wiring stack, the multilayer wiring stack comprising alternating layers of dielectric material and wiring; bonding a capping layer to the multilayer wiring stack, in which the capping layer includes a single crystal silicon dielectric layer; forming a via hole within the capping layer, in which the via hole extends to a first wiring layer of the multilayer wiring stack; forming an electrically conductive via within the via hole and electrically coupled to the first wiring layer; and forming a circuit element on a surface of the capping layer, in which the circuit element is directly electrically coupled to the electrically conductive via.
-
-
-
-
-
-
-
-
-
Search Results
21
records
(took 0.014 seconds)
