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    Symmetrical Clock Distribution in Multi-Stage High Speed Data Conversion Circuits
    11.
    发明申请
    Symmetrical Clock Distribution in Multi-Stage High Speed Data Conversion Circuits 失效
    多级高速数据转换电路中的对称时钟分配

    公开(公告)号：US20080175277A1

    公开(公告)日：2008-07-24

    申请号：US12014094

    申请日：2008-01-15

    Applicant: Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

    Inventor： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

    IPC: H04J3/02

    CPC classification number: H04J3/0685 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

    Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

    Abstract translation: 提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。 数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。 对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。 时钟分配电路接收并对称地将时钟信号分配给数据转换电路。 耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。 分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

    Symmetrical clock distribution in multi-stage high speed data conversion circuits
    12.
    发明授权
    Symmetrical clock distribution in multi-stage high speed data conversion circuits 失效
    多级高速数据转换电路中的对称时钟分布

    公开(公告)号：US07319706B2

    公开(公告)日：2008-01-15

    申请号：US10609058

    申请日：2003-06-28

    Applicant: Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

    Inventor： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

    IPC: H04J3/02

    CPC classification number: H04J3/0685 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

    Abstract: The present invention provides a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

    Abstract translation: 本发明提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。 数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。 对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。 时钟分配电路接收并对称地将时钟信号分配给数据转换电路。 耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。 分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

    Delay generator with symmetric signal paths
    13.
    发明授权
    Delay generator with symmetric signal paths 有权
    具有对称信号路径的延迟发生器

    公开(公告)号：US07319351B2

    公开(公告)日：2008-01-15

    申请号：US11084369

    申请日：2005-03-18

    Applicant: Bo Zhang ,  Guangming Yin

    Inventor： Bo Zhang ,  Guangming Yin

    IPC: H03L7/06

    CPC classification number: H03H11/265 ,  H03H11/126

    Abstract: A delay circuit generates delayed signals. The delay circuit includes a delay locked loop having an input terminal coupled to a periodic input signal, the delay locked ioop generating one or more delayed periodic signals and a control signal for controlling the time delay between the periodic input signal and the delayed periodic signals. The delay circuit also includes a controlled delay circuit for generating one or more delayed periodic signals. The controlled delay circuit has an input terminal for receiving at least one of the delayed periodic signals from the delay locked loop and a delay control terminal coupled to the control signal from the delay locked ioop for controlling the time delay between the delayed periodic input signal received from the delay locked loop and the one or more delayed periodic signals generated by the controlled delay circuit.

    Abstract translation: 延迟电路产生延迟信号。 延迟电路包括具有耦合到周期性输入信号的输入端的延迟锁定环，延迟锁定产生一个或多个延迟周期信号，以及用于控制周期性输入信号和延迟周期信号之间的时间延迟的控制信号。 延迟电路还包括用于产生一个或多个延迟周期信号的受控延迟电路。 受控延迟电路具有用于接收来自延迟锁定环路的延迟周期信号中的至少一个的输入端子和与来自延迟锁存器的控制信号耦合的延迟控制端子，用于控制接收到的延迟的周期性输入信号之间的时间延迟 从延迟锁定环和由受控延迟电路产生的一个或多个延迟周期信号。

    Delay generator
    14.
    发明申请
    Delay generator 有权
    延迟发生器

    公开(公告)号：US20050162208A1

    公开(公告)日：2005-07-28

    申请号：US11084369

    申请日：2005-03-18

    Applicant: Bo Zhang ,  Guangming Yin

    Inventor： Bo Zhang ,  Guangming Yin

    IPC: H03H11/12 ,  H03H11/26

    CPC classification number: H03H11/265 ,  H03H11/126

    Abstract: A delay circuit generates delayed signals. The delay circuit includes a delay locked loop having an input terminal coupled to a periodic input signal, the delay locked ioop generating one or more delayed periodic signals and a control signal for controlling the time delay between the periodic input signal and the delayed periodic signals. The delay circuit also includes a controlled delay circuit for generating one or more delayed periodic signals. The controlled delay circuit has an input terminal for receiving at least one of the delayed periodic signals from the delay locked loop and a delay control terminal coupled to the control signal from the delay locked ioop for controlling the time delay between the delayed periodic input signal received from the delay locked loop and the one or more delayed periodic signals generated by the controlled delay circuit.

    Abstract translation: 延迟电路产生延迟信号。 延迟电路包括具有耦合到周期性输入信号的输入端的延迟锁定环，延迟锁定产生一个或多个延迟周期信号，以及用于控制周期性输入信号和延迟周期信号之间的时间延迟的控制信号。 延迟电路还包括用于产生一个或多个延迟周期信号的受控延迟电路。 受控延迟电路具有用于接收来自延迟锁定环路的延迟周期信号中的至少一个的输入端子和与来自延迟锁存器的控制信号耦合的延迟控制端子，用于控制接收到的延迟的周期性输入信号之间的时间延迟 从延迟锁定环和由受控延迟电路产生的一个或多个延迟周期信号。

    Delay generator with controlled delay circuit
    15.
    发明授权
    Delay generator with controlled delay circuit 失效
    具延时电路的延时发生器

    公开(公告)号：US06870415B2

    公开(公告)日：2005-03-22

    申请号：US10243086

    申请日：2002-09-12

    Applicant: Bo Zhang ,  Guangming Yin

    Inventor： Bo Zhang ,  Guangming Yin

    IPC: H03H11/12 ,  H03H11/26

    CPC classification number: H03H11/265 ,  H03H11/126

    Abstract: A delay circuit generates delayed signals. The delay circuit includes a delay locked loop having an input terminal coupled to a periodic input signal, the delay locked loop generating one or more delayed periodic signals and a control signal for controlling the time delay between the periodic input signal and the delayed periodic signals. The delay circuit also includes a controlled delay circuit for generating one or more delayed periodic signals. The controlled delay circuit has an input terminal for receiving at least one of the delayed periodic signals from the delay locked loop and a delay control terminal coupled to the control signal from the delay locked loop for controlling the time delay between the delayed periodic input signal received from the delay locked loop and the one or more delayed periodic signals generated by the controlled delay circuit.

    Abstract translation: 延迟电路产生延迟信号。 延迟电路包括延迟锁定环路，其具有耦合到周期性输入信号的输入端子，延迟锁定环路产生一个或多个延迟周期信号，以及用于控制周期性输入信号和延迟周期信号之间的时间延迟的控制信号。 延迟电路还包括用于产生一个或多个延迟周期信号的受控延迟电路。 受控延迟电路具有用于接收来自延迟锁定环路的延迟周期信号中的至少一个的输入端子和耦合到来自延迟锁定环路的控制信号的延迟控制端子，用于控制接收到的延迟周期性输入信号之间的时间延迟 从延迟锁定环和由受控延迟电路产生的一个或多个延迟周期信号。

    SIGNAL DELAY STRUCTURE IN HIGH SPEED BIT STREAM DEMULTIPLEXER
    17.
    发明申请
    SIGNAL DELAY STRUCTURE IN HIGH SPEED BIT STREAM DEMULTIPLEXER 有权
    信号延迟结构在高速位流解复用器

    公开(公告)号：US20100054384A1

    公开(公告)日：2010-03-04

    申请号：US12613740

    申请日：2009-11-06

    Applicant: Jun Cao ,  Guangming Yin

    Inventor： Jun Cao ,  Guangming Yin

    IPC: H04L7/00

    CPC classification number: G06F1/10 ,  H03K5/135 ,  H04J3/0629 ,  H04L7/0008 ,  H04L25/14

    Abstract: A signal delay structure and method of reducing skew between clock and data signals in a high-speed serial communications interface includes making a global adjustment to the clock signal in the time domain to compensate for a component of the skew that is common between the clock and all data signals. This can include skew caused by the variation in frequency of the input clock from a nominal value, misalignment between the phase of the clock and data generated at the source of the two signals. The global adjustment is made through a delay component that is common to all of the clock signal lines for which skew with data signals is to be compensated. A second level adjustment is made that compensates for the component of the skew that is common to the clock and a subset of the data signals.

    Abstract translation: 在高速串行通信接口中减少时钟和数据信号之间的偏差的信号延迟结构和方法包括对时域中的时钟信号进行全局调整，以补偿时钟和 所有数据信号。 这可能包括由输入时钟从标称值的频率变化引起的偏斜，时钟相位与在两个信号的源极产生的数据之间的偏移。 通过延迟分量进行全局调整，该延迟分量对于要对其进行补偿的具有数据信号的偏斜的所有时钟信号线是共同的。 进行第二级调整，补偿时钟共同的偏斜分量和数据信号的子集。

    Adaptable voltage control for a variable gain amplifier
    18.
    发明授权
    Adaptable voltage control for a variable gain amplifier 有权
    适用于可变增益放大器的电压控制

    公开(公告)号：US07262659B2

    公开(公告)日：2007-08-28

    申请号：US11559195

    申请日：2006-11-13

    Applicant: Mario Caresosa ,  Guangming Yin

    Inventor： Mario Caresosa ,  Guangming Yin

    IPC: H03F3/45

    CPC classification number: H03F3/4569 ,  H03F3/45197 ,  H03F3/45744 ,  H03F2200/78 ,  H03F2203/45074 ,  H03F2203/45086 ,  H03F2203/45482 ,  H03F2203/45486 ,  H03G1/0088 ,  H03G3/3036 ,  H03G3/3052

    Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.

    Abstract translation: 一种用于自适应地控制可变增益放大器（VGA）的方法和装置。 VGA的操作被分为低增益模式和高增益模式，并且自适应地感测VGA当前正在操作的模式。 将门限电压与VGA的控制电压进行比较; 如果VGA当前处于低增益模式并且控制电压高于阈值电压，则VGA从低增益模式切换到高增益模式; 如果VGA当前处于高增益模式并且控制电压低于阈值电压，则VGA从高增益模式切换到低增益模式。

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