公开(公告)号：US20090273998A1

公开(公告)日：2009-11-05

申请号：US12114966

申请日：2008-05-05

Applicant: Hongtau Mu ,  Nian Yang ,  Fan Wan Lai ,  Guowei Wang

Inventor： Hongtau Mu ,  Nian Yang ,  Fan Wan Lai ,  Guowei Wang

IPC: G11C7/06

CPC classification number: G11C7/067 ,  G11C7/062 ,  G11C7/08 ,  G11C2207/063

Abstract: A memory device includes a sense amplifier to sense the state of a bitcell. The sense amplifier includes two input terminals connected via a switch. One of the input terminals is connected to a node, whereby a current through the node represents a difference in current drawn by a bitcell and a reference current. During a first phase, the switch between the input terminals of the sense amplifier is closed, so that a common voltage is applied to both input terminals. During a second phase, the switch is opened, and the sense amplifier senses a state of information stored at the bitcell based on the current through the node. By using the switch to connect and disconnect the inputs of the sense amplifier in the two phases, the accuracy and speed with which the state of the information stored at the bitcell can be determined is improved.

Abstract translation: 存储器件包括用于感测位单元的状态的读出放大器。 读出放大器包括通过开关连接的两个输入端。 一个输入端子连接到一个节点，由此通过该节点的电流表示由位单元和参考电流所画出的电流差。 在第一阶段期间，读出放大器的输入端之间的开关闭合，使得两个输入端施加公共电压。 在第二阶段期间，开关被打开，并且感测放大器基于通过节点的电流来感测存储在位单元的信息的状态。 通过使用开关来连接和断开两相中的读出放大器的输入，可以确定存储在位单元中的信息的状态的精度和速度。

公开(公告)号：US07443732B2

公开(公告)日：2008-10-28

申请号：US11229527

申请日：2005-09-20

Applicant: Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael A. VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Quang Le

Inventor： Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael A. VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Quang Le

IPC: G11C11/34

CPC classification number: G11C5/147 ,  G11C16/12

Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

Abstract translation: 提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括接收包含要在阵列中被编程的预定数量的位的编程窗口，并且确定在存储器阵列中哪个预定位数被编程。 预定数量的位同时被编程到阵列中的对应存储器单元。 同时验证阵列中预定位数的编程状态。

公开(公告)号：US20080130371A1

公开(公告)日：2008-06-05

申请号：US11950811

申请日：2007-12-05

Applicant: Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

Inventor： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

IPC: G11C16/12 ,  G11C16/28

CPC classification number: G11C7/1039 ,  G11C8/08 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2245

Abstract: A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710). For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200). For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

公开(公告)号：US06542435B1

公开(公告)日：2003-04-01

申请号：US09531871

申请日：2000-03-21

Applicant: Guowei Wang

Inventor： Guowei Wang

IPC: G11C800

CPC classification number: G11C8/18

Abstract: A method and apparatus ensure equal address transition detection (ATD) pulse width for all address and chip enable transitions. Address buffer signals from one end of an integrated circuit are combined to form a first combined signal. Address buffer signals and a chip enable signal from a second end of the integrated circuit are combined to form a second combined signal. The two combined signals are logically combined to form a first edge of an ATD pulse. A feedback signal controls the second edge of the ATD pulse for all input signal transitions.

Abstract translation: 一种方法和装置确保所有地址和芯片使能转换的等同地址转换检测（ATD）脉冲宽度。 来自集成电路一端的地址缓冲器信号被组合以形成第一组合信号。 来自集成电路的第二端的地址缓冲器信号和芯片使能信号被组合以形成第二组合信号。 两个组合信号被逻辑地组合以形成ATD脉冲的第一边缘。 反馈信号控制所有输入信号转换的ATD脉冲的第二个边沿。

公开(公告)号：US06366513B1

公开(公告)日：2002-04-02

申请号：US09483381

申请日：2000-01-12

Applicant: Guowei Wang

Inventor： Guowei Wang

IPC: G11C708

CPC classification number: G11C7/062 ,  G11C7/067

Abstract: A memory integrated circuit (100) includes a core cell array (102) having a plurality of core cells for storing data in one of a plurality of states, a plurality of power supply buses (140, 142, 144, 146) including a sensing power supply bus (144) and a sensing ground bus (146) dedicated to sensing states of core cells. The integrated circuit firther includes a sense threshold generating circuit (126) which generates a sense threshold signal in response to a power supply potential on the sensing power supply bus and a ground potential of the sensing ground bus. The integrated circuit still further includes a plurality of sense amplifiers (108) which detect the states of core cells in relation to the sense threshold signal. The sense amplifiers are coupled to the sensing power supply bus and the sensing ground bus so that substantially all power supply noise at the plurality of sense amplifiers and the sense threshold generator is common node noise.

Abstract translation: 存储器集成电路（100）包括具有多个核心单元的核心单元阵列（102），用于以多个状态之一存储数据;多个电源总线（140,142,144,146），包括感测 电源总线（144）和专用于感测核心单元的状态的感测接地总线（146）。 集成电路包括感测阈值产生电路（126），其响应于感测电源总线上的电源电位和感测接地总线的接地电位而产生感测阈值信号。 集成电路还包括多个读出放大器（108），其检测与感测阈值信号相关的核心单元的状态。 感测放大器耦合到感测电源总线和感测接地总线，使得多个感测放大器和感测阈值发生器处的基本上所有的电源噪声都是公共节点噪声。

公开(公告)号：US07804715B2

公开(公告)日：2010-09-28

申请号：US12114966

申请日：2008-05-05

Applicant: Hongtau Mu ,  Nian Yang ,  Fan Wan Lai ,  Guowei Wang

Inventor： Hongtau Mu ,  Nian Yang ,  Fan Wan Lai ,  Guowei Wang

IPC: G11C16/06

CPC classification number: G11C7/067 ,  G11C7/062 ,  G11C7/08 ,  G11C2207/063

Abstract: A memory device includes a sense amplifier to sense the state of a bitcell. The sense amplifier includes two input terminals connected via a switch. One of the input terminals is connected to a node, whereby a current through the node represents a difference in current drawn by a bitcell and a reference current. During a first phase, the switch between the input terminals of the sense amplifier is closed, so that a common voltage is applied to both input terminals. During a second phase, the switch is opened, and the sense amplifier senses a state of information stored at the bitcell based on the current through the node. By using the switch to connect and disconnect the inputs of the sense amplifier in the two phases, the accuracy and speed with which the state of the information stored at the bitcell can be determined is improved.

Abstract translation: 存储器件包括用于感测位单元的状态的读出放大器。 读出放大器包括通过开关连接的两个输入端。 一个输入端子连接到一个节点，由此通过该节点的电流表示由位单元和参考电流所画出的电流差。 在第一阶段期间，读出放大器的输入端之间的开关闭合，使得两个输入端施加公共电压。 在第二阶段期间，开关被打开，并且感测放大器基于通过节点的电流来感测存储在位单元的信息的状态。 通过使用开关来连接和断开两相中的读出放大器的输入，可以确定存储在位单元中的信息的状态的精度和速度。

公开(公告)号：US07345916B2

公开(公告)日：2008-03-18

申请号：US11423638

申请日：2006-06-12

Applicant: Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

Inventor： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

IPC: G11C16/04 ,  G11C16/06 ,  G11C5/14 ,  G11C7/00

CPC classification number: G11C7/1039 ,  G11C8/08 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2245

Abstract: A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710).For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200).For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

公开(公告)号：US20070291550A1

公开(公告)日：2007-12-20

申请号：US11423638

申请日：2006-06-12

Applicant: Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

Inventor： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

IPC: G11C11/34 ,  G11C16/04 ,  G11C8/00 ,  G11C7/00 ,  G11C16/06

CPC classification number: G11C7/1039 ,  G11C8/08 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2245

Abstract: A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710).For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200).For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

公开(公告)号：US07295475B2

公开(公告)日：2007-11-13

申请号：US11229664

申请日：2005-09-20

Applicant: Takao Akaogi ,  Guowei Wang

Inventor： Takao Akaogi ,  Guowei Wang

IPC: G11C11/34

CPC classification number: G11C16/0491 ,  G11C16/0475 ,  G11C16/10

Abstract: Non-volatile memory, such as Flash memory, is programmed by writing a window of information to memory. The programmed/non-programmed state of each memory cell may be dynamically determined for each window and stored as an indication bit. These techniques can provide for improved average power drain and a reduced maximum current per window during programming.

公开(公告)号：US07196938B1

公开(公告)日：2007-03-27

申请号：US11229530

申请日：2005-09-20

Applicant: Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Aaron Lee

Inventor： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Aaron Lee

IPC: G11C16/04

CPC classification number: G11C16/12

Abstract: A non-volatile memory cell array, such as a Flash NOR array, is programmed by applying voltages to bit lines that connect to memory cells in the memory cell array. A first bit line corresponding to a first memory cell in the memory array may be turned on to perform a first programming operation for the first memory cell and second bit line corresponding to a second memory cell in the memory array may be turned on to perform a second programming operation that is configured to complete after the first programming operation. The turning on/off of the first and second bit lines may be overlapped to share charge between the first and second bit lines. This overlapping can reduce wasted power and decrease programming pulse overshoot problems.

Abstract translation: 诸如闪存NOR阵列的非易失性存储单元阵列通过将电压施加到连接到存储单元阵列中的存储单元的位线来编程。 对应于存储器阵列中的第一存储器单元的第一位线可以被接通以对第一存储器单元执行第一编程操作，并且可以打开与存储器阵列中的第二存储器单元相对应的第二位线来执行 第二编程操作被配置为在第一编程操作之后完成。 第一和第二位线的导通/截止可以重叠以在第一和第二位线之间共享电荷。 这种重叠可以减少浪费的功率并减少编程脉冲过冲问题。