公开(公告)号：US07269673B2

公开(公告)日：2007-09-11

申请号：US10781405

申请日：2004-02-18

申请人： Ook Kim ,  Eric Lee ,  Gyudong Kim ,  Zeehoon Jang ,  Baegin Sung ,  Nam Hoon Kim ,  Gijung Ahn ,  Seung Ho Hwang

发明人： Ook Kim ,  Eric Lee ,  Gyudong Kim ,  Zeehoon Jang ,  Baegin Sung ,  Nam Hoon Kim ,  Gijung Ahn ,  Seung Ho Hwang

IPC分类号： G06F13/38

CPC分类号： G06F13/385

摘要： A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information. The cable can include a radiation-emitting element and circuitry for generating driving signals for causing the radiation-emitting element to produce an appropriate color, brightness, and/or blinking pattern.

摘要翻译： 包括用于向用户或外部设备断言信息的电路的电缆以及包括这种电缆的系统。 电缆可以包括导体，存储电缆数据的存储器和经配置以通过访问至少一些电缆数据来响应于在至少一个导体上接收到的请求的电路，并且将所访问的数据串行地认定到至少一个导体 （例如，用于传输到外部设备）。 本发明的其他方面是用于访问存储在电缆中并且可选地使用数据（例如，实现均衡）的电缆数据的方法。 电缆数据可以表示电缆类型，等级，速度，长度和阻抗的全部或一些，日期代码，频率相关衰减表，远端串扰和EMI相关系数，共模辐射，内部对 歪斜等信息。 电缆可以包括辐射发射元件和用于产生用于使辐射发射元件产生适当的颜色，亮度和/或闪烁图案的驱动信号的电路。

公开(公告)号：US20050195894A1

公开(公告)日：2005-09-08

申请号：US10794015

申请日：2004-03-05

申请人： Ook Kim ,  Gyudong Kim

发明人： Ook Kim ,  Gyudong Kim

IPC分类号： H03D1/04 ,  H03K5/01

CPC分类号： H04L25/03019

摘要： In preferred embodiments, an adaptive equalization circuit including at least two equalization filters (each for equalizing a signal transmitted over a multi-channel serial link) and control circuitry for generating an equalization control signal for use by all the filters. The control circuitry generates the control signal in response to an equalized signal produced by one of the filters, and asserts the control signal to all the filters. Preferably, one filter generates an equalized fixed pattern signal in response to a fixed pattern signal (e.g., a clock signal), each other filter equalizes a data signal, and the control circuitry generates the control signal in response to the equalized fixed pattern signal. In other embodiments, the invention is an adaptive equalization circuit including an equalization filter and circuitry for generating a control signal for the filter in response to a signal indicative of a predetermined fixed pattern, a receiver including an adaptive equalization circuit, a system including such a receiver, and a method for adaptive equalization of signals received over a multi-channel serial link.

摘要翻译： 在优选实施例中，自适应均衡电路包括至少两个均衡滤波器（每个用于均衡通过多通道串行链路传输的信号）和用于产生用于所有滤波器的均衡控制信号的控制电路。 控制电路响应于由滤波器之一产生的均衡信号而产生控制信号，并将控制信号置为全部滤波器。 优选地，一个滤波器响应于固定模式信号（例如，时钟信号）产生均衡的固定模式信号，每个其他滤波器均衡数据信号，并且控制电路响应于均衡的固定模式信号而产生控制信号。 在其他实施例中，本发明是一种自适应均衡电路，包括均衡滤波器和用于响应于指示预定固定模式的信号产生用于滤波器的控制信号的电路，包括自适应均衡电路的接收机， 接收机和用于通过多声道串行链路接收的信号的自适应均衡的方法。

公开(公告)号：US06809567B1

公开(公告)日：2004-10-26

申请号：US09989645

申请日：2001-11-20

申请人： Ook Kim ,  Hung Sung Li ,  Inyeol Lee ,  Gyudong Kim ,  Yongman Lee

发明人： Ook Kim ,  Hung Sung Li ,  Inyeol Lee ,  Gyudong Kim ,  Yongman Lee

IPC分类号： H03L700

CPC分类号： H03K23/542 ,  G06F1/06 ,  H03K5/15013 ,  H03L7/0891 ,  H03L7/0995

摘要： A system and method for multiple-phase clock generation is disclosed. In one embodiment, a multiple-stage voltage controlled oscillator (“VCO”) transmits a plurality of clock phases to a clock divider circuit which produces the desired number of clock phase outputs. The clock divider circuit in this embodiment includes a state machine, e.g., a modified Johnson counter, that provides a plurality of divided down clock phases, each of which is connected to a separate modified shift register. Each modified shift register contains D-type flip-flops and each D-type flip-flop provides a separate clock phase output. In one embodiment the number of clock phase outputs of the multiple-phase clock is a function of the number of VCO clock phases times the number of desired states in the modified Johnson counter.

摘要翻译： 公开了一种用于多相时钟产生的系统和方法。 在一个实施例中，多级压控振荡器（“VCO”）将多个时钟相位发送到产生期望数量的时钟相位输出的时钟分频器电路。 该实施例中的时钟分频器电路包括一个状态机，例如修改的约翰逊计数器，其提供多个划分的下降时钟相位，每个分频下降沿连接到单独的修改的移位寄存器。 每个修改的移位寄存器包含D型触发器，每个D型触发器提供单独的时钟相位输出。 在一个实施例中，多相时钟的时钟相位输出的数量是VCO时钟相位数乘以修改的约翰逊计数器中期望状态数量的函数。

公开(公告)号：US06717478B1

公开(公告)日：2004-04-06

申请号：US09989587

申请日：2001-11-20

申请人： Ook Kim ,  Hung Sung Li ,  Inyeol Lee ,  Gyudong Kim ,  Yongman Lee

发明人： Ook Kim ,  Hung Sung Li ,  Inyeol Lee ,  Gyudong Kim ,  Yongman Lee

IPC分类号： H03B2700

CPC分类号： H03L7/0995 ,  H03B5/24 ,  H03B27/00 ,  H03L7/0891

摘要： A voltage controlled oscillator (“VCO”) circuit capable of generating signals with reduced jitter and/or low-phase noise is provided. One embodiment provides a plurality of cascaded VCO cells, where each VCO cell can include a source coupled differential pair, a bias transistor connected to the differential pair for biasing the differential pair, a resistive load pair connected to the differential pair, and a voltage controlled capacitor pair or varactor pair connected to the differential pair. The varactors provide control over the frequency of the oscillations produced by the VCO circuit in combination with a control voltage. A phase frequency detector combined with a charge pump and loop filter provide the control voltage.

摘要翻译： 提供了能够产生具有降低的抖动和/或低相位噪声的信号的压控振荡器（“VCO”）电路。 一个实施例提供多个级联VCO单元，其中每个VCO单元可以包括源极耦合差分对，连接到差分对的偏置晶体管，用于偏置差分对，连接到差分对的电阻负载对，以及电压控制 电容器对或变容二极管对连接到差分对。 变容二极管提供对由VCO电路产生的振荡频率与控制电压的组合的控制。 与电荷泵和环路滤波器组合的相位检波器提供控制电压。

公开(公告)号：US06693985B2

公开(公告)日：2004-02-17

申请号：US10043886

申请日：2001-10-26

申请人： Hung Sung Li ,  Ook Kim

发明人： Hung Sung Li ,  Ook Kim

IPC分类号： H04L700

CPC分类号： H03L7/091 ,  H03L7/0814 ,  H03L7/087 ,  H04L7/0337

摘要： Embodiments of a clock and data recovery method and apparatus include receiving a multi-channel serial digitally encoded signal and converting the received signal to digital data, or set of binary characters. One embodiment includes determining whether a phase of a sampling circuit is appropriate to sample meaningful data from a received signal; if the phase of the sampling circuit is not appropriate, the phase is shifted so that sampling occurs earlier or later for the received signal. The determination is based, in one embodiment, on the order and value of the samples taken, which indicate whether the samples are taken too close to a transition of the received signal.

摘要翻译： 时钟和数据恢复方法和装置的实施例包括接收多通道串行数字编码信号并将接收的信号转换为数字数据或二进制字符的集合。 一个实施例包括确定采样电路的相位是否适合于从接收信号中采样有意义的数据; 如果采样电路的相位不合适，则相位被移位，使得针对接收信号更早或更晚地进行采样。 在一个实施例中，该确定基于所采集的样本的顺序和值，其指示采样是否太接近于接收到的信号的转变。

公开(公告)号：US6121818A

公开(公告)日：2000-09-19

申请号：US970350

申请日：1997-11-14

申请人： Ook Kim ,  Jong-Kee Kwon ,  Jong-Ryul Lee ,  Chang-Jun Oh ,  Won-Chul Song

发明人： Ook Kim ,  Jong-Kee Kwon ,  Jong-Ryul Lee ,  Chang-Jun Oh ,  Won-Chul Song

IPC分类号： H03D7/00 ,  H03D7/14 ,  G06F7/44

CPC分类号： H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03D2200/0088

摘要： The present invention discloses a mixer using a replica voltage-current converter, and more particularly a mixer using the replica voltage-current (V-I) converter of the present invention, which feedbacks the output current of the replica voltage-current converter using an additional amplifier so as to improve the linearity thereof by the gain of the amplifier because the conventional mixer operating at a high speed dissipates a lot of electrical power to have low output impedance.

摘要翻译： 本发明公开了一种使用复制电压 - 电流转换器的混频器，特别是使用本发明的复制电压 - 电流（VI）转换器的混频器，其使用附加放大器来反馈复制电压 - 电流转换器的输出电流 以便通过放大器的增益来提高其线性度，因为常规的混频器以高速度运行，将大量的电能消耗到具有低的输出阻抗。

公开(公告)号：US06845461B1

公开(公告)日：2005-01-18

申请号：US09989590

申请日：2001-11-20

申请人： Ook Kim

发明人： Ook Kim

IPC分类号： G06F13/14 ,  G06F13/42

CPC分类号： G06F13/4278

摘要： A system and method for embedding at least one clock signal into bus lines that also carry data signals at other times to enable a high-speed bus is disclosed. Each bus line is used for carrying both clock and data information at different times. Data signals, which may be either encoded or not, are carried through a subset of the bus lines through a mapping scheme that maps the data information to the bus lines at each data transfer while the clock signals are carried in the remaining bus lines. Various mapping schemes are possible.

摘要翻译： 公开了一种用于将至少一个时钟信号嵌入总线的系统和方法，该总线还在其它时间承载数据信号，以实现高速总线。 每条总线用于在不同时间承载时钟和数据信息。 数据信号可以是编码的，也可以是编码的，通过映射方案，通过映射方案，将数据信息映射到总线，同时在剩余的总线中携带时钟信号。 各种映射方案是可能的。

公开(公告)号：US6069537A

公开(公告)日：2000-05-30

申请号：US124142

申请日：1998-07-29

申请人： Ook Kim ,  Jong Kee Kwon ,  Jong Ryul Lee ,  Chang Jun Oh ,  Won Chul Song ,  Kyung Soo Kim

发明人： Ook Kim ,  Jong Kee Kwon ,  Jong Ryul Lee ,  Chang Jun Oh ,  Won Chul Song ,  Kyung Soo Kim

IPC分类号： H04B1/00 ,  H04B1/40 ,  H04L27/00 ,  H04L27/20 ,  H04L27/32

CPC分类号： H04L27/0008 ,  H04B1/406 ,  H04L27/2071 ,  H04B1/00

摘要： A double mode modulator, particularly, for a portable telephone, which is adapted to realize both digital and analog modulations and have a low phase noise and a reduced locking time with a device readily integrated in an integrated circuit, including: a frequency synthesizer for synthesizing a particular frequency from an external reference clock signal; a digital modulator for performing a quadrature modulation for an output signal of the frequency synthesizer; and an analog modulator for performing a frequency modulation for the output signal of the frequency synthesizer.

摘要翻译： 一种双模式调制器，特别是用于便携式电话，其适于实现数字和模拟调制，并且具有低相位噪声和减少的锁定时间，其中易于集成在集成电路中的器件包括：用于合成的频率合成器 来自外部参考时钟信号的特定频率; 用于对频率合成器的输出信号执行正交调制的数字调制器; 以及用于对频率合成器的输出信号执行频率调制的模拟调制器。

公开(公告)号：US20150015078A1

公开(公告)日：2015-01-15

申请号：US14376151

申请日：2012-03-27

申请人： Ook Kim

发明人： Ook Kim

IPC分类号： G05F5/00 ,  H03H17/02

CPC分类号： G05F5/00 ,  H03H17/0248 ,  H04L25/0276 ,  H04L25/0282 ,  H04L25/03146

摘要： The present specification provides a cable and a compensation method for transmitting a high speed signal and delivering power. The cable according to one embodiment disclosed in the present specification interconnects a first device and a second device, the cable comprising: a power line for transmitting power from the first device to the second device; and a voltage restorer for restoring voltage loss of the power receiving side of the second device generated based on the voltage drop relevant to the power line.

摘要翻译： 本说明书提供了用于传输高速信号和传送电力的电缆和补偿方法。 根据本说明书中公开的一个实施例的电缆互连第一设备和第二设备，该电缆包括：用于从第一设备向第二设备发送电力的电力线; 以及电压恢复器，用于恢复基于与电力线相关的电压降产生的第二装置的电力接收侧的电压损失。

公开(公告)号：US20070085988A1

公开(公告)日：2007-04-19

申请号：US11254296

申请日：2005-10-19

申请人： Ook Kim

发明人： Ook Kim

IPC分类号： G03B27/42

CPC分类号： G03F7/70425 ,  G03F7/2028 ,  H01L21/682

摘要： The present invention relates to a method for exposing an edge of a semiconductor wafer in photolithographic processes, and an OF (Orientation Flatness) detecting system provided with a WEE (Wafer Edge Exposure) apparatus. According to the present invention, a notch-aligned wafer can be treated by a WEE process on a wafer chuck of an OF detecting system, without waiting for its patterning exposure process to be performed first. Thus, the total processing time in photolithographic processes can be decreased.

摘要翻译： 本发明涉及一种用于在光刻工艺中曝光半导体晶片的边缘的方法，以及设置有WEE（晶片边缘曝光）装置的OF（取向平坦度）检测系统。 根据本发明，可以通过在OF检测系统的晶片卡盘上的WEE处理来对凹口对准的晶片进行处理，而不等待首先执行其图案化曝光处理。 因此，可以减少光刻工艺中的总处理时间。