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    TCAM-driven RRAM
    12.
    发明授权
    TCAM-driven RRAM 有权

    公开(公告)号：US10418103B1

    公开(公告)日：2019-09-17

    申请号：US15958903

    申请日：2018-04-20

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Brent Buchanan ,  John Paul Strachan ,  Le Zheng ,  Catherine Graves

    IPC: G11C15/00 ,  G11C15/04 ,  G11C13/00 ,  G11C7/06

    Abstract: According to examples, an apparatus may include a ternary content addressable memory (TCAM) including a plurality of TCAM bit cells connected in a row along a match line. Each of the TCAM bit cells may store a bit of a TCAM word and the TCAM bit cells may drive a digital signal over the match line in response to a search word matching the TCAM word. The apparatus may include a resistive random-access memory (RRAM) comprising a row of RRAM bit cells connected to the TCAM via the match line. Each of the RRAM bit cells may store a bit of a RRAM word. The RRAM bit cells may output the RRAM word in response to the TCAM bit cells driving the digital signal over the match line.

    Accelerator for k-means clustering with memristor crossbars
    13.
    发明授权
    Accelerator for k-means clustering with memristor crossbars 有权

    公开(公告)号：US10380386B1

    公开(公告)日：2019-08-13

    申请号：US15966600

    申请日：2018-04-30

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： John Paul Strachan ,  Catherine Graves ,  Suhas Kumar

    IPC: G06G7/16 ,  H03M1/00 ,  G11C13/00 ,  G06F16/35

    Abstract: A crossbar array includes a number of memory elements. A vector input register has N voltage inputs to the crossbar array. A vector output register has M voltage outputs from the crossbar array. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A clustering processor is electronically coupled to the ADC and to the DAC. The clustering processor is configured to program columns of the crossbar array with a set of k cluster center values; apply voltages to rows of the crossbar array where the applied voltages represent a set of data values; and determine a minimum distance of each data value to each k cluster center values based on the voltage output from the output register of each of the plurality of the programmed columns.

    Hardware accelerators for calculating node values of neural networks
    14.
    发明授权
    Hardware accelerators for calculating node values of neural networks 有权

    公开(公告)号：US10332592B2

    公开(公告)日：2019-06-25

    申请号：US15570951

    申请日：2016-03-11

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： John Paul Strachan ,  Brent Buchanan ,  Le Zheng

    IPC: G11C11/54 ,  G06F9/06 ,  G06N3/063 ,  G11C13/00 ,  G11C7/10 ,  G06N3/04

    Abstract: Examples herein relate to hardware accelerators for calculating node values of neural networks. An example hardware accelerator may include a crossbar array programmed to calculate node values of a neural network and a current comparator to compare an output current from the crossbar array to a threshold current according to an update rule to generate new node values. The crossbar array has a plurality of row lines, a plurality of column lines, and a memory cell coupled between each unique combination of one row line and one column line, where the memory cells are programmed according to a weight matrix. The plurality of row lines are to receive an input vector of node values, and the plurality of column lines are to deliver an output current to be compared with the threshold current.

    DOUBLE BIAS MEMRISTIVE DOT PRODUCT ENGINE FOR VECTOR PROCESSING
    15.
    发明申请
    DOUBLE BIAS MEMRISTIVE DOT PRODUCT ENGINE FOR VECTOR PROCESSING 审中-公开

    公开(公告)号：US20190035463A1

    公开(公告)日：2019-01-31

    申请号：US16148468

    申请日：2018-10-01

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Miao Hu ,  Jianhua Yang ,  John Paul Strachan ,  Ning Ge

    IPC: G11C13/00 ,  G06F17/16

    Abstract: A double bias dot-product engine for vector processing is described. The dot product engine includes a crossbar array having N×M memory elements to store information corresponding to values contained in an N×M matrix, each memory element being a memristive storage device. First and second vector input registers including N voltage inputs, each voltage input corresponding to a value contained in a vector having N×1 values. The vector input registers are connected to the crossbar array to supply voltage inputs to each of N row electrodes at two locations along the electrode. A vector output register is also included to receive voltage outputs from each of M column electrodes.

    Ternary content addressable memories
    20.
    发明授权
    Ternary content addressable memories 有权

    公开(公告)号：US09847132B1

    公开(公告)日：2017-12-19

    申请号：US15222234

    申请日：2016-07-28

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Le Zheng ,  Brent Buchanan ,  John Paul Strachan

    IPC: G11C15/00 ,  G11C15/04

    CPC classification number: G11C15/046 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/79

    Abstract: An example ternary content addressable memory. A bit cell of the memory may include first and second memristors, with a first terminal of the first memristor being connected to a first terminal of the second memristor via a node, a second terminal of the first memristor being switchably connected to a first data line, and a second terminal of the second memristor being switchably connected to a second data line. The bit cell may also include a match-line transistor that is connected between a first rail and a match line, with a gate of the match-line transistor being connected to the node.

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