公开(公告)号：US09727462B2

公开(公告)日：2017-08-08

申请号：US14435167

申请日：2013-01-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Vincent Nguyen ,  Binh Nguyen ,  William C. Hallowell ,  Raghavan V. Venugopal

IPC: G06F3/06 ,  G06F12/0804 ,  G11C14/00

CPC classification number: G06F12/0804 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0685 ,  G06F2003/0691 ,  G06F2212/1032 ,  G06F2212/202 ,  G11C14/0018

Abstract: During runtime of a system, a memory controller is caused to relinquish control of a memory module that includes a volatile memory and a non-volatile memory. After the triggering, an indication is activated to the memory module, the indication causing a backup operation in the memory module, the backup operation being controlled by an internal controller in the memory module, and the backup operation involving a transfer of data from the volatile memory to the non-volatile memory in the memory module.

公开(公告)号：US10775859B2

公开(公告)日：2020-09-15

申请号：US15273860

申请日：2016-09-23

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Vincent Nguyen ,  Michael T. Gill

IPC: G06F1/20 ,  G06F9/445 ,  G06F1/3203 ,  G06F1/3206 ,  G06F9/52 ,  G06F9/46 ,  G06F9/48

Abstract: A method may include assigning a core identifier of an active core to an idle core. After synchronizing the active core and idle core, the active core is inactivated.

公开(公告)号：US10740270B2

公开(公告)日：2020-08-11

申请号：US15578521

申请日：2015-06-26

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Kevin G. Depew ,  Vincent Nguyen ,  Scott P. Faasse ,  Robert E. Van Cleve

IPC: G06F13/40 ,  G06F13/12 ,  G06F11/30 ,  G06F11/34

Abstract: Example implementations relate to a self-tune controller. For example, the self-tune controller may poll, via an out-of-band data stream, low-level operation information about a processor or a bus of a computing system under a present workload. At least some of the low-level operation information may be descriptive of a nature of traffic on the bus. The self-tune controller may program, via an out-of-band control signal, a setting of the computing system for the present workload based on the low-level operation information.

公开(公告)号：US10509449B2

公开(公告)日：2019-12-17

申请号：US15644121

申请日：2017-07-07

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Vincent Nguyen ,  Robert E. Van Cleve

IPC: G06F1/00 ,  G06F1/20 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3287

Abstract: In one example in accordance with the present disclosure, a method may comprise collecting environment information for a processor, determining a maximum power level for the processor and setting a frequency level and a core-to-frequency ratio that maintains the maximum power for the processor. The frequency level and the core-to-frequency are respectively controlled by a programmable frequency register and a programmable core register. The method may comprise receiving a die temperature corresponding to the processor, determining that the die temperature exceeds a temperature corresponding to the processor and adjusting the maximum power to a level that maintains the temperature.

公开(公告)号：US20190171257A1

公开(公告)日：2019-06-06

申请号：US16271047

申请日：2019-02-08

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Earl Moore ,  Vincent Nguyen

IPC: G06F1/18 ,  A47B88/49 ,  G11B33/00

Abstract: An example mounting assembly is provided herein. The mounting assembly includes a first cage, a second cage, a rail member, a rigid cable member, a latch member, and a lock mechanism. The rail member to move the first cage and the second cage between an installed position, an access position, and a transitional position. The rigid cable member to move with the first cage and the second cage along the rail member. The latch member to retain the first cage and the second cage in the installed position. The lock mechanism to hold the second cage in the access position.

公开(公告)号：US20190163366A1

公开(公告)日：2019-05-30

申请号：US16247318

申请日：2019-01-14

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Vincent Nguyen ,  Thierry Fevrier ,  David Engler

IPC: G06F3/06 ,  G06F9/50

Abstract: An example device in accordance with an aspect of the present disclosure includes a plurality of memory segments corresponding to at least one memory channel of a computing system that is to receive a memory module. A performance attribute of an Advanced Configuration and Power Interface (ACPI) table is set to indicate performance of at least one of the plurality of memory segments, and is usable for memory allocation by an operating system memory manager.

公开(公告)号：US20180024768A1

公开(公告)日：2018-01-25

申请号：US15549724

申请日：2015-02-13

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Vincent Nguyen ,  Jeffrey A. Plank ,  Hai Ngoc Nguyen ,  Han Wang ,  Patrick A. Raymond ,  Raghavan V. Venugopal ,  Barry L. Olawsky

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F1/263 ,  G06F1/28 ,  G06F1/30 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0679 ,  G06F11/1441 ,  G06F11/2015 ,  G06F12/16

Abstract: Example implementations relate to partitioning memory modules into volatile and non-volatile portions. For example, a system includes a memory controller to partition a memory module into a non-volatile portion and a volatile portion and to identify persistent data to be backed up during a power loss condition. The memory controller is further to transfer the persistent data from the volatile portion of the memory module to the non-volatile portion of the memory module, in response to the power loss condition.

公开(公告)号：US20240204433A1

公开(公告)日：2024-06-20

申请号：US18065946

申请日：2022-12-14

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Kuan-Wei Chen ,  Vincent Nguyen ,  Ku-Hsu Nien ,  Jui Lin Chen ,  Hsueh Yu Chao

IPC: H01R12/72 ,  H01R12/70 ,  H01R12/71

CPC classification number: H01R12/721 ,  H01R12/7011 ,  H01R12/716

Abstract: A modular riser card, an electronic device having a modular riser card, and a method of determining a type of modular riser card pin connection are disclosed. The modular riser card includes a circuit board and a removable connector assembly. The circuit board includes a first receptacle having a plurality of first pins. The removable connector assembly includes a connector body defining a second receptacle having a plurality of second pins, and an opening formed in the connector body adjacent to the second receptacle. The connector body is mounted on the circuit board such that the first receptacle protrudes through the opening and is aligned with the second receptacle. The first and second receptacles form a riser card connector that is configured to removably receive an expansion card of an electronic device.

公开(公告)号：US11940859B2

公开(公告)日：2024-03-26

申请号：US16194017

申请日：2018-11-16

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Robert E. Van Cleve ,  Vincent Nguyen

IPC: G06F1/324

CPC classification number: G06F1/324

Abstract: A method of adjusting core and un-core operating frequencies of two or more processors of a server includes determining core and un-core operating frequency variations versus power consumption limit variations of the two or more processors. The method also includes determining two or more first power consumption levels associated with the two or more processors. Each one of the two or more processors run at essentially a same target core operating frequency and at a same target un-core operating frequency at the respective first power consumption level of the processor. The method further includes adjusting the core and un-core operating frequencies of the two or more processors by setting a power consumption limit of each one of the two or more processors at the respective first power consumption level of the processor.

公开(公告)号：US10957999B1

公开(公告)日：2021-03-23

申请号：US16669908

申请日：2019-10-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Norton ,  Vincent Nguyen

IPC: H01R12/59 ,  H01R27/02 ,  H01R25/00 ,  G05B19/042

Abstract: One or more stacking cabled I/O slots may be installed in a stacked arrangement on a computing device, such as in an I/O expansion socket of a computing device motherboard. Slot detection and population logic associated with each of the one or more stacking cabled I/O slots enables signaling from each installed stacking cabled I/O slot, in order for its presence and location relative to any other installed stacking cabled I/O slot to be identified to and recognized by the computing device. High speed data signals through an installed stacking cabled I/O slot are coupled to the computing device via a cable, while power and logic signals are exchanged between the computing device and the one or more stacking cabled I/O slots via connections to the I/O expansion socket.