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公开(公告)号：US20180350433A1
公开(公告)日：2018-12-06
申请号：US15570980
申请日：2015-09-25
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Miao Hu , Zhiyong Li , John Paul Strachan
CPC classification number: G11C13/0007 , G06G7/16 , G11C5/05 , G11C13/0023 , G11C13/003 , G11C13/0069 , G11C2213/79
Abstract: A crossbar array, comprises a plurality of row lines, a plurality of column lines intersecting the plurality of row lines at a plurality of intersections, a plurality of junctions coupled between the plurality of row lines and the plurality of column lines at a portion of the plurality of intersections, and a plurality of diagonal control lines coupled to the plurality of junctions. Each junction comprises a resistive memory element and a transistor, and the junctions are positioned to calculate a matrix multiplication of a first matrix and a second matrix.
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公开(公告)号：US20180301189A1
公开(公告)日：2018-10-18
申请号：US15570932
申请日：2015-08-07
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Miao Hu , John Paul Strachan , Zhiyong Li , R. Stanley Williams
Abstract: A crossbar array, comprises a plurality of row lines, a plurality of column lines intersecting the plurality of row lines at a plurality of intersections, and a plurality of junctions coupled between the plurality of row lines and the plurality of column lines at a portion of the plurality of intersections. Each junction comprises a resistive memory element, and the junctions are positioned to calculate a matrix multiplication of a first matrix and a second matrix.
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公开(公告)号：US09911788B2
公开(公告)日：2018-03-06
申请号：US15308923
申请日：2014-05-05
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Jianhua Yang , Ning Ge , Zhiyong Li
CPC classification number: H01L27/2418 , H01L27/2409 , H01L45/00 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/16
Abstract: A selector with an oxide-based layer includes an oxide-based layer that has a first region and a second region. The first region contains a metal oxide in a first oxidation state, and the second region contains the metal oxide in a second oxidation state. The first region also forms a part of each of two opposite faces of the oxide-based layer.
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公开(公告)号：US20170110515A1
公开(公告)日：2017-04-20
申请号：US15128244
申请日：2014-04-10
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Jianhua Yang , Gary Gibson , Zhiyong Li
CPC classification number: H01L27/2481 , G11C13/004 , G11C13/0069 , H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L45/04 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/145 , H01L45/146
Abstract: A 1-Selector n-Resistor memristive device includes a first electrode, a selector, a plurality of memristors, and a plurality of second electrodes. The selector is coupled to the first electrode via a first interface of the selector. Each memristor is coupled to a second interface of the selector via a first interface of each memristor. Each second electrode is coupled to one of the memristors via a second interface of each memristor.
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公开(公告)号：US11043265B2
公开(公告)日：2021-06-22
申请号：US16072575
申请日：2016-02-12
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Zhiyong Li , Lu Zhang , Minxian Zhang
Abstract: An example device in accordance with an aspect of the present disclosure includes an active oxide layer to form and dissipate a conductive bridge. The conductive bridge is to dissipate spontaneously within a relaxation time to enable the memory device to self-refresh according to volatile behavior in response to the input voltage being below a threshold corresponding to disregarding sneak current and noise of a crossbar array in which the memory device is to operate. The conductive bridge is to persist beyond the relaxation time to enable the memory device to retain programming for neuromorphic computing training according to non-volatile behavior of the memory device in response to the input voltage not being below the threshold.
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Patent Agency Ranking
公开(公告)号：US10410716B2
公开(公告)日：2019-09-10
申请号：US15570980
申请日：2015-09-25
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Miao Hu , Zhiyong Li , John Paul Strachan
Abstract: A crossbar array, comprises a plurality of row lines, a plurality of column lines intersecting the plurality of row lines at a plurality of intersections, a plurality of junctions coupled between the plurality of row lines and the plurality of column lines at a portion of the plurality of intersections, and a plurality of diagonal control lines coupled to the plurality of junctions. Each junction comprises a resistive memory element and a transistor, and the junctions are positioned to calculate a matrix multiplication of a first matrix and a second matrix.
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公开(公告)号：US10337950B2
公开(公告)日：2019-07-02
申请号：US15397798
申请日：2017-01-04
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Tahir Cader , Zhiyong Li , John Franz
Abstract: Examples herein relate to detecting a coolant leak. For example, a system includes a nanosensor coupled to an airflow channel in a server. The nanosensor provides a resistance measurement to a controller. The system includes the controller coupled to the nanosensor. The controller detects the coolant leak based on the resistance measurement from the nanosensor.
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公开(公告)号：US10026896B2
公开(公告)日：2018-07-17
申请号：US15500050
申请日：2015-02-13
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Warren Jackson , Jianhua Yang , Kyung Min Kim , Zhiyong Li
Abstract: A multilayered memristor includes a semiconducting n-type layer, a semiconducting p-type layer, and a semiconducting intrinsic layer. The semiconducting n-type layer includes one or both of anion vacancies and metal cations. The semiconducting p-type layer includes one or both of metal cation vacancies and anions. The semiconducting intrinsic layer is coupled between the n-type layer and the p-type layer to form an electrical series connection through the n-type layer, the intrinsic layer, and the p-type layer.
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公开(公告)号：US20180075904A1
公开(公告)日：2018-03-15
申请号：US15557872
申请日：2015-04-27
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Ning Ge , Jianhua Yang , Zhiyong Li , R. Stanley Williams
CPC classification number: G11C13/004 , G11C13/003 , G11C13/0069 , G11C2213/74 , G11C2213/76 , H01L27/2418 , H01L27/2427 , H01L27/2463 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/147
Abstract: A memristive crossbar array is described. The crossbar array includes a number of row lines and a number of column lines intersecting the row lines to form a number of cross points. A number of memristor cells are coupled between the row lines and the column lines at the cross points. A memristor cell includes a memristive memory element to store information and multiple selectors electrically coupled to the memristive memory element. The multiple selectors are to provide access to the memristive memory element.
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20.发明申请公开(公告)号：US20170271589A1
公开(公告)日：2017-09-21
申请号：US15329801
申请日：2015-01-26
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Minxian Max Zhang , Jianhua Yang , Zhiyong Li , R. Stanley Williams
CPC classification number: H01L45/146 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/1633 , H01L45/1641
Abstract: A resistive memory array includes a plurality of resistive memory devices. A sneak path current in the resistive memory array is reduced when a negative temperature coefficient of resistance material is incorporated in series with a negative differential resistance selector that is in series with a memristor switching material at a junction formed at a cross-point between two conductors of one of the plurality of resistive memory devices.
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