公开(公告)号：US20150348763A1

公开(公告)日：2015-12-03

申请号：US14727265

申请日：2015-06-01

Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION

Inventor： Masahito MORI ,  Naoyuki KOFUJI ,  Naoshi ITABASHI

IPC: H01J37/32

CPC classification number: H01J37/32798 ,  C23F4/00 ,  H01J37/32009 ,  H01J37/32183 ,  H01J37/32706 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136 ,  H01L21/32137 ,  H01L29/517

Abstract: The invention provides a plasma processing apparatus and a dry etching method for etching a multilayered film structure having steps with high accuracy. The plasma processing apparatus comprises a vacuum reactor, a lower electrode placed within a processing chamber of the vacuum reactor and having a wafer to be etched mounted on the upper surface thereof, bias supplying units and for supplying high frequency power for forming a bias potential to the lower electrode, a gas supply means for feeding reactive gas into the processing chamber, an electric field supplying means through for supplying a magnetic field for generating plasma in the processing chamber, and a control unit for controlling the distribution of ion energy in the plasma being incident on the wafer via the high frequency power.

Abstract translation: 本发明提供一种用于蚀刻具有高精度步骤的多层膜结构的等离子体处理装置和干蚀刻方法。 等离子体处理装置包括真空反应器，放置在真空反应器的处理室内的下电极，并且其上表面具有要蚀刻的晶片，偏压供应单元和用于提供用于形成偏置电位的高频功率 下电极，用于将反应性气体供给到处理室中的气体供给装置，用于在处理室中提供用于产生等离子体的磁场的电场供给装置，以及用于控制等离子体中的离子能分布的控制单元 通过高频功率入射到晶片上。

公开(公告)号：US20140175534A1

公开(公告)日：2014-06-26

申请号：US13958685

申请日：2013-08-05

Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION

Inventor： Naoyuki KOFUJI ,  Nobuyuki NEGISHI ,  Hiroaki ISHIMURA

IPC: H01L27/105

CPC classification number: H01L27/11582 ,  H01L21/31144 ,  H01L27/11556 ,  H01L27/11575 ,  H01L29/66833 ,  H01L29/7926

Abstract: In a process of dividing gates of multi-layered films in fabricating a NAND flash memory having a three-dimensional structure, a pattern is prevented from deforming and falling. A ratio of a length L to a height h of control gate groups configuring a memory cell of the flash memory is set to be less than 1.65 which is a range in which buckling does not occur. It is desirable that a ratio of a length L to a width W of the control gate groups is set to be less than 16.5.

Abstract translation: 在制造具有三维结构的NAND闪存的过程中，分隔多层膜的栅极的过程中，防止图案变形和下降。 将构成闪速存储器的存储单元的控制栅极组的长度L与高度h的比率设定为小于1.65，这是不发生翘曲的范围。 希望将控制栅极组的长度L与宽度W的比率设定为小于16.5。